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Project Specification
Project Overview
  • Product: q.bit modular educational robotics controller
  • Status: Draft — schematic implementation starting
  • Purpose: ESP32-S3 controller and shared power/data backplane for eight removable modules.
Intended Use
  • Educational and modular robotics development.
  • Removable modules attach vertically to magnetic pogo docking zones.
  • Production-intent SMT assembly with repeated docking cycles.
What the Device Should Do
  • Accept USB-C power and support native ESP32-S3 USB programming.
  • Supply a regulated shared 5 V rail operated under a 6.8 A firmware allocation; the power stage remains an 8 A-class design target but does not provide a guaranteed 7.5 A or 8 A hardware ceiling.
  • Protect each modular port with an approximately 2 A current limit.
  • Provide shared 3.3 V I2C SDA/SCL and one dedicated SIG line per port.
  • Provide WiFi and BLE through the ESP32-S3 module.
Main Features
  • ESP32-S3-WROOM-1-N8R8.
  • Eight identical 5-contact magnetic pogo connectors in a 4 × 2 top-side grid.
  • One top-edge USB-C connector; all other components mounted underneath.
  • Six-layer controlled-impedance PCB.
  • Side-accessible RESET and BOOT controls.
System Architecture

Diagram


USB-C PD + USB 2.0 CH224K 20 V negotiation 20 V to 5 V synchronous buck; 6.8 A firmware allocation 8 x 2 A port eFuses 8 magnetic pogo ports 5 V to 3.3 V logic regulator ESP32-S3-WROOM-1-N8R8 Shared SDA and SCL 8 dedicated SIG lines
Hardware Subsystems
USB-C and PD input
  • One USB-C receptacle on the top edge.
  • CH224K requests a 20 V fixed PD profile.
  • USB D+/D- connect to ESP32-S3 native USB through ESD protection and optional series damping resistors.
  • Input protection includes VBUS TVS, fuse/eFuse and bulk capacitance.
Main 5 V conversion
  • Target output: 5 V with a 6.8 A firmware-controlled operational allocation. The hardware is an 8 A-class design target, not a guaranteed 7.5 A or 8 A current ceiling.
  • Preliminary implementation: LM5148 synchronous buck controller with external MOSFETs, designed from 20 V PD input.
  • With the actual 6 mOhm shunt/current-sense network, estimated LM5148 equivalent DC current-limit onset is 7.34-11.79 A (9.40 A typical). This is an onset estimate, not a guaranteed output-current or short-circuit ceiling, because the relevant comparator/propagation delay lacks a guaranteed maximum.
  • At 90% efficiency and the 6.8 A allocation (34 W output), expected 20 V input current is approximately 1.89 A; a 20 V / 3 A or better PD source remains recommended for transient and conversion margin.
  • The originally proposed TPS563201 is retained only as a possible low-power logic regulator candidate; it cannot generate the high-current 5 V actuator rail.
Port protection
  • One independently current-limited 5 V eFuse/load switch per port, nominal limit 2 A.
  • Firmware must enforce the 6.8 A global operational allocation and must not assume all eight ports can simultaneously draw 2 A. The present LM5148 network does not guarantee a precise aggregate hardware ceiling.
  • Fault reporting and controllable enable are preferred.
Logic power
  • Separate 3.3 V regulator for ESP32-S3 and logic, sized for at least 1 A peak with appropriate transient margin.
Compute and communication
  • ESP32-S3-WROOM-1-N8R8 with native USB programming.
  • Shared I2C bus with one pull-up pair near the MCU.
  • Eight independent protected SIG GPIO lines.
Interfaces and Connections
Each port uses exactly:
  1. 5 V protected output
  2. GND
  3. SDA (3.3 V I2C)
  4. SCL (3.3 V I2C)
  5. Dedicated SIG
Power and Runtime Expectations
  • External USB-C PD source only; no battery in the current scope.
  • Required adapter profile: 20 V / 3 A minimum recommended.
  • 5 V operational allocation: 6.8 A total under firmware management, with approximately 2 A intended per active port. No guaranteed 7.5 A or 8 A aggregate hardware ceiling is claimed.
  • Logic must remain stable during servo transients and port faults.
Power Tree and Power Budget

Table


RailLoadsContinuous design targetNotes
20 V PDMain buck + logic losses~1.89 A at 34 W/90%Size input path for at least 3 A
5 V actuatorController plus ports6.8 A firmware allocationLM5148 onset estimate 7.34-11.79 A, 9.40 A typical; not a guaranteed ceiling
3.3 V logicESP32-S3, I2C, indicators, controls1 A regulator targetAllow WiFi current transients
Manufacturing and Assembly Expectations
  • Six-layer PCB, nominal 1.6 mm FR-4.
  • Matte black solder mask and light silkscreen.
  • Top side contains only USB-C and eight pogo docking connectors.
  • Bottom-side SMT electronics; assembly must support high-current thermal copper and via arrays.
  • Selected pogo connector: SAMZO PR5L5015-5P-C-H, LCSC C41361293, specified 5 contacts, 12 V and 2 A contact rating.
  • Exact footprint and magnet/mechanical geometry remain blocked pending an authoritative manufacturer drawing or datasheet.
Firmware-Relevant Hardware Requirements
  • Native USB-Serial/JTAG programming through the USB-C connector.
  • Side-accessible RESET (EN) and BOOT (GPIO0) buttons.
  • Individual port enable/fault control where GPIO availability permits; otherwise use GPIO expanders only if required by final pin budget.
  • Port-load scheduling/power management to enforce the 6.8 A operational allocation.
Physical Design Expectations
  • Exact board size: 155 mm × 85 mm, rounded rectangular outline.
  • Eight top-side docking zones arranged four columns by two rows.
  • ESP32 mounted underneath at an edge with antenna facing outward.
  • No copper, traces, vias, components, magnets or mounting metal in the module antenna keep-out on any layer.
  • Low component-height and mechanical-clearance zones beneath docking hardware.
Important Design Decisions
  • Six layers selected for USB signal integrity, RF return paths and high-current power distribution.
  • 20 V PD followed by a high-current 5 V synchronous buck is required to support the 6.8 A operational allocation with conversion and transient margin; direct 5 V USB-C is not suitable for this power architecture.
  • USB-C is shared for power negotiation and ESP32 native USB data/programming.
  • All non-docking electronics are mounted on the bottom.
Assumptions
  • A 20 V / 3 A USB-PD adapter is available.
  • The 2 A pogo rating applies to each electrical contact; the VCC contact operates at its stated limit and therefore has limited current margin.
  • Modules tolerate shared 3.3 V I2C signaling and include unique addresses or otherwise avoid bus-address conflicts.
  • SIG electrical direction is not yet fixed; protection will be selected once module behavior is confirmed.
Change Notes
  • Replaced the stale 5 V / 8 A guarantee with a 6.8 A firmware operational allocation. The LM5148 current-limit onset is estimated at 7.34-11.79 A (9.40 A typical) and is not a guaranteed aggregate hardware ceiling.
  • Changed board requirement from four to six copper layers.
  • Selected SAMZO PR5L5015-5P-C-H / LCSC C41361293 pogo connector.
  • Confirmed top-side restriction: USB-C and eight docking connectors only.
  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • USB-C and PD input

  • Main 5 V conversion

  • Port protection

  • Logic power

  • Compute and communication

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes