Your proposed U12 rotation is noted, but I could not apply it because tool access ended.
Current verified state:
U12 remains at (−52.5, 29.0) mm, Bottom, 180°.
JPORT1 was moved to (−52.5, 15.0) mm, Top, 0°.
The U12/JPORT1 overlap is cleared.
U12-specific DRC shows no overlap, bounds, pad-access, keepout, protected-copper, trace, or invalid-layer findings.
Routing preflight has only the unrelated via-at-SMD advisory.
Auto-routing did not proceed; 239 airwires remain.
A new generic placement error appeared during the route launch and must be diagnosed.
Before changing U12 to 80°, the exact orientation must be checked against pad containment and the antenna edge: rotating from 180° to 80° may point the antenna sideways or place pads outside the board. The next pass should apply 80° as a candidate, run U12 pad/boundary and six-layer antenna-keepout checks, and retain it only if those pass.
Rev A is not production-ready. The architecture is directionally workable, but the live PCB has 319 unrouted airwires, a confirmed U12 edge-placement error, 10 redundant-trace warnings, unresolved USB differential-pair verification, and incomplete production part locking. These are manufacturing blockers, not optional polish.
Executive decision
Keep USB-C PD at an elevated voltage and convert locally to 5V_MAIN. Do not change to nominal 5 V / 5 A direct USB-C input. Standard interoperable USB-C fixed 5 V operation is normally limited to 3 A; a design that assumes 5 A at 5 V would depend on a nonstandard or tightly controlled source/cable ecosystem. For this product, option A is technically preferable to option B.
However, 20 V is not automatically the optimum contract for the stated approximately 25 W, two-servo use case. A 9 V or 12 V PD contract with a suitably selected integrated buck may reduce conversion ratio, switching stress, and implementation complexity. This alternative must be evaluated with a measured servo transient profile and an updated regulator loss/thermal analysis before changing the current design.
1. CRITICAL - MUST CHANGE
1.1 Complete and validate PCB routing
Location: Entire PCB.
Current design: Live checks report 319 airwires.
Problem: The board is electrically incomplete and cannot be fabricated as a functional design.
Exact recommended change: Finish routing using controlled power-plane strategy for 20V_IN, 5V_MAIN, and port outputs; route USB D+/D- as a verified 90 ohm differential pair; then run full DRC, return-path, current-density, and connectivity checks.
Reason: Unrouted nets are a hard production blocker.
Current design: Edge-placement check reports an error.
Problem: The module antenna geometry/edge relationship is not validated and can compromise RF performance or violate the module placement requirement.
Exact recommended change: Reposition/orient U12 so the antenna end and keepout comply with Espressif's module placement guidance; keep copper, traces, components, and enclosure metal out of the antenna keepout on every relevant layer.
Reason: RF performance and certification assumptions depend on correct antenna placement.
1.3 Establish a real worst-case servo power budget
Current design: The design target is approximately two servos / 25 W, but exact servo model, stall current, startup pulse, pulse duration, and simultaneous-event assumptions are not locked.
Problem: Regulator, connector, copper, fuse, shunt, and transient-capacitance adequacy cannot be proven without worst-case load data.
Exact recommended change: Measure or obtain authoritative maximum current waveforms for the selected servos. Budget continuous, startup, reversal, and stall events separately; include ESP32 and module loads; reflect output power through converter efficiency to the PD input; verify every series element and thermal path.
Reason: Typical current is not a safe basis for actuator power design.
1.4 Add aggregate hardware current enforcement or explicitly derate the product
Location: Main 5 V power path and eight MP5073 channels U4-U11.
Current design: Per-port protection exists, but firmware allocation is being used as part of the system-level load strategy.
Problem: Eight individually permitted channels can exceed the upstream converter, connector, or PD source capability. Firmware is not a safety-rated hardware current limiter.
Exact recommended change: Add a hardware-enforced aggregate limit in the main 5 V path, or set each channel limit and product specification so the sum of all simultaneous hardware limits cannot exceed the validated upstream capacity. Document fault behavior and recovery.
Reason: Prevents source collapse, converter overload, overheating, and repeated brownouts under multi-port faults.
1.5 Verify MP5073 current-limit and thermal implementation
Location: U4-U11 and associated resistors/capacitors.
Current design: Eight protected 5 V outputs are provided.
Problem: Exact programmed limit, tolerance, startup behavior into capacitive loads, short-circuit response, dissipation, and thermal coupling are not yet evidenced for the chosen module/servo loads.
Exact recommended change: Calculate each programmed limit from the authoritative datasheet, including tolerance; validate hot-plug and short-circuit waveforms; check package thermal rise at sustained overload; ensure bulk capacitance does not cause nuisance trips.
Reason: Per-port eFuses must protect both the connector and shared supply without blocking legitimate servo transients.
1.6 Verify connector and pogo current capability
Location: JPORT1-JPORT8 and mating module contacts.
Current design: Five-pin magnetic pogo docking interface carries 5 V, GND, SIG, SDA, and SCL.
Problem: Contact current rating, temperature rise, contact resistance over life, misalignment behavior, and make/break sequencing are not confirmed in the audit evidence.
Exact recommended change: Obtain manufacturer ratings for the complete mated interface, not only the PCB half. Validate voltage drop and temperature rise at maximum port current and after lifecycle cycling. Confirm GND/5 V sequencing is safe during angled docking.
Reason: The connector is in the actuator current path and may be the limiting element.
1.7 Lock production components and remove ambiguous generics
Location: BOM.
Current design: 151 instances / 24 unique part types. The BOM includes 43 generic capacitors, 52 generic resistors, and one generic inductor; current review previously identified 76 instances without locked production MPNs.
Problem: Values alone do not lock dielectric, voltage rating, tolerance, pulse rating, package, DCR, saturation current, lifecycle, or supply chain.
Exact recommended change: Assign approved MPNs and alternates to every production-critical passive, especially L2, current-setting resistors, feedback/compensation components, USB parts, and high-current input/output capacitors. Re-run BOM availability checks.
Reason: An unlocked BOM is not reproducible or safe to release.
2. IMPORTANT - SHOULD CHANGE
2.1 Re-evaluate 20 V versus 9 V or 12 V PD
Current design: CH224K requests 20 V and LM5148 converts to 5 V.
Recommendation: KEEP the elevated-voltage PD concept for interoperability, but compare 9 V, 12 V, and 20 V using measured load, cable current, converter efficiency, switch stress, inductor size, thermal concentration, and available PD adapters. A lower elevated voltage may be a better Rev A simplification if it still delivers transient power with margin.
2.2 Remove redundant copper
Location: Ten traces currently flagged as redundant.
Recommendation: Delete or reconnect the reported stubs/islands/loops before final DRC. Do not waive them without visual review.
2.3 Validate input protection coordination
Location: J1, F1, D1, U1, Q1/Q2, U2 input.
Recommendation: Verify surge clamp voltage versus absolute maximum ratings, fuse clearing versus TVS energy, reverse-current behavior, inrush, and hot-plug stress at the selected PD contract.
2.4 Validate 5V_MAIN transient network
Location: U2 output and C14-C17 plus local port capacitance.
Recommendation: Use measured servo step loads to calculate allowed droop, required effective capacitance after MLCC DC-bias derating, control-loop response, and damping. Confirm the ESP32 3.3 V rail remains inside limits during servo events.
2.5 Verify AP63203 3.3 V rail margin
Location: U3 and its inductor/capacitors.
Recommendation: Budget ESP32 Wi-Fi transmit peaks plus TCA9548A, LEDs, protection leakage, and attached logic. Verify peak current, inductor saturation, output ripple, and startup sequencing from 5V_MAIN.
2.6 Verify USB 2.0 routing and source coexistence
Location: J1, D2, U12 and USB data nets.
Recommendation: Confirm connector pin mapping, ESD placement, continuous reference plane, pair spacing/width, length skew, and no stubs. Resolve the legacy pair-mapping warning rather than merely waiving it.
2.7 Define module EEPROM electrical contract
Location: U13 channels and external modules.
Recommendation: Specify 24LC02/24LC02B supply voltage, fixed address straps, write-protect state, required decoupling, maximum channel capacitance, module pull-up policy, memory map, and hot-plug behavior. Avoid uncontrolled duplicate pull-ups on each mux channel.
Recommendation: Add labeled test points and define current-limited bring-up and functional test procedures.
3. KEEP - CORRECT DECISIONS
KEEP - no change required: ESP32-S3-WROOM-1-N8R8 as the main controller, subject to correct RF placement and strap verification.
KEEP - no change required: One TCA9548A channel per docking port. This isolates same-address EEPROMs and same-address runtime I2C devices.
KEEP - no change required: Per-port 5 V protection using U4-U11, subject to verified current limits and thermals.
KEEP - no change required: Universal port pin intent: 5V, GND, SIG, SDA, SCL.
KEEP - no change required: SIG1-SIG8 assigned to ADC1-capable ESP32 GPIOs, assuming the final pin table and boot-state behavior remain documented.
KEEP - no change required: USB data ESD protection close to the connector, provided the final physical route is compliant.
KEEP - no change required: Six-layer construction for dense power, USB, RF, and eight-port routing, provided the stackup includes continuous reference planes.
4. POWER ARCHITECTURE DECISION
Option A: USB-C PD -> 20 V -> LM5148 -> 5V_MAIN
Decision: KEEP for the current revision direction, with verification and possible optimization to 9 V or 12 V.
Advantages:
Interoperable path to more than 15 W from ordinary USB-C PD sources.
Lower cable current for a given power level than 5 V delivery.
Provides input headroom for a regulated 5 V actuator rail.
Disadvantages:
High conversion ratio and concentrated switching/thermal design burden.
Greater sensitivity to layout, switch-node EMI, input transients, and component selection.
LM5148 implementation may be oversized for a tightly constrained approximately 25 W product.
Option B: USB-C PD -> 5 V / approximately 5 A directly -> 5V_MAIN
Decision: REJECT as the general production architecture.
Reason: Standard USB-C fixed 5 V delivery is normally limited to 3 A. A nominal 5 V / 5 A requirement is not broadly interoperable and would require a controlled nonstandard/programmed source ecosystem. It also loses voltage headroom for cable/contact drop and servo transients.
Recommended optimization study
Before release, compare 9 V, 12 V, and 20 V contracts with a regulator selected specifically for the verified load. Do not change the schematic solely for simplification until the servo transient data and PD source compatibility matrix are complete.
5. FINAL RECOMMENDED ARCHITECTURE
Diagram
6. PCB CHANGES CHECKLIST
Route all 319 airwires.
Correct U12 antenna edge placement and keepout.
Preserve a continuous reference plane under USB; no plane splits or stubs.
Resolve USB differential-pair mapping and impedance checks.
Remove or justify all 10 redundant traces.
Use wide pours and multiple vias for 20V_IN, 5V_MAIN, GND, and port power paths.
Verify current density and voltage drop from buck output to every port.
Minimize U2 hot-loop and switch-node area; keep sensitive feedback away from SW.
Place effective bulk capacitance close to the shared port distribution point.
Confirm thermal copper and via arrays for U2 and U4-U11.
Keep I2C channel pull-ups and decoupling close to U13/port branches.
Keep protection devices close to the external connector they protect.
Add labeled test points for all critical rails and control/fault signals.
Run final DRC, ERC, SI, PI, manufacturability, and assembly checks.
7. FINAL BOM CHANGES
Remove
No active IC is proven unnecessary yet.
Remove redundant copper-related artifacts from layout, not BOM.
Add
Hardware aggregate current limiting/protection if upstream limiting cannot be guaranteed by the validated converter implementation.
Test points for critical rails and signals.
Any damping/bulk capacitance demonstrated necessary by transient testing.
Replace or lock
Replace generic L2 with a fully specified production MPN.
Lock all production-critical generic resistors and capacitors to approved MPNs and alternates.
Replace U2/20 V contract only if the 9 V or 12 V optimization study proves a simpler, cooler, fully compatible solution.
Keep
U12 ESP32-S3-WROOM-1-N8R8.
U13 TCA9548APWR.
U4-U11 MP5073GG-Z architecture, pending current-limit and thermal validation.
Unverified eFuse and pogo thermal/current behavior.
Ten redundant traces requiring review.
Incomplete production MPN locking and sourcing validation.
Optional improvements
Optimize 20 V to 9 V or 12 V if measurements prove a simpler solution.
Add enhanced telemetry per port.
Add extra debug/status indicators if board area permits.
Reduce BOM diversity after electrical validation.
Practical Rev A recommendation
Do not release the current PCB. Keep the elevated-voltage USB-C PD architecture rather than adopting 5 V / 5 A direct input. First lock the servo load envelope, validate the upstream and per-port hardware current limits, correct U12 RF placement, finish routing, resolve USB and redundant-copper checks, lock all critical passive MPNs, and pass full electrical/thermal bring-up on prototypes. Treat a 9 V or 12 V PD redesign as a focused cost/thermal optimization study, not as a prerequisite unless the current 20 V converter fails validation.
Evidence status
Live project inspection on 2026-09-08: 151 components, 24 unique part types, 319 airwires, one U12 edge-placement error, and 10 redundant-trace warnings.
Schematic architecture inspected by an independent executor: CH224K elevated-voltage PD, LM5148 5 V rail, AP63203 3.3 V rail, eight MP5073 port channels, TCA9548A mux, ESP32-S3, and protected USB data.
Exact servo model/current waveform, mated pogo current rating, MP5073 programmed thresholds/thermal results, and final USB impedance are NEEDS VERIFICATION.