PCB Design for Coal Boiler Controller

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Current project state before this request:
  • Project: 7segment driver uyT3
  • Existing design appears to be a 7-segment/TM1637-style board, not the requested boiler controller.
  • Existing components: 46 total, including TM1637-1, resistors, capacitors, connectors, and pin sockets.
  • Existing nets: 18.
  • The requested change is effectively a full redesign/replacement into a 230VAC ESP32-S3 boiler controller PCB.
What remains to be done when execution is available:
  1. Replace the current schematic with the new controller architecture.
  2. Add and wire:
    • Adafruit Feather ESP32-S3 socket
    • HLK-PM01 5V AC/DC module
    • ULN2003A driver
    • 3x PT1000 divider/filter inputs
    • 5x optotriac/triac output channels
    • CH5 fuse, BT138, SRD-05VDC relay, BC547 driver, NE555 watchdog
    • PC817 zero-cross detector
    • All screw terminals, debug header, LEDs, snubbers, decoupling, pullups, and protection parts
  3. Verify all ICs against datasheets before wiring, especially:
    • Feather ESP32-S3 pinout/current limits
    • ULN2003A
    • MOC3041 / MOC3042M
    • BT136 / BT138
    • HLK-PM01
    • NE555
    • PC817
    • SRD-05VDC-SL-C relay
  4. Perform a power budget check for the 5V rail. The HLK-PM01 is only 600mA, and relay coil + optocouplers + LEDs + Feather load may be close enough that this must be verified before committing.
  5. Run ERC/review and fix all unresolved schematic violations.
  6. Only after the schematic is clean, proceed to layout:
    • Set PCB to 100mm x 80mm, 2-layer FR4.
    • Place LV section on left, HV section on right.
    • Keep minimum 4mm creepage between HV and LV copper.
    • Place TRIACs in a bottom-edge row with heatsink/mounting features.
    • Apply HV trace width rules: mains ≥1.5mm, load outputs ≥2mm, LV ≥0.3mm.
    • Add mounting holes, silkscreen zone boundary, warning labels, and connector labels.
  7. Route and run DRC until clean.
Important engineering note: this is a mains-voltage boiler controller, so the design must be reviewed carefully for creepage, clearance, fusing, isolation, thermal behavior, and fail-safe operation before manufacturing.
Check power budget
Save requirements note
Find main parts
Review GPIO map
Identify safety issues
DIO
SEG8
GRID6
SEG7
R2
Resistance
10kΩ
GND
SEG6
SEG4
C4
Capacitance
100pF
VCC
GRID4
SEG8
GRID5
SEG1
SEG6
GRID1
C3
Capacitance
100pF
GRID2
SEG2
SEG2
SEG3
GRID3
GRID5
R1
Resistance
10kΩ
SEG5
SEG4
J2
GRID4
GND
CLK
SEG3
GRID2
C1
Capacitance
1uF
GRID1
VCC
GRID3
SEG7
SEG5
SEG1
C5
Capacitance
100uF
J1


7segment driver uyT3

7segment driver uyT3 thumbnail
Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Digi-Key

$0.28–$0.51

LCSC

$0.29

Mouser

$0.51

Controls