Pi Zero Replacement Discussion

flux

Execution is now blocked because there are no available ACUs.
What I accomplished:
  • Started manual reconstruction from the verified BOM/CPL/PDF/Gerber references.
  • Chose to reconstruct the original Pi Zero baseline first, then migrate that verified baseline to CM4/native Ethernet.
  • Added the original power input / regulator block components:
    • U10 power input connector
    • F1 input fuse
    • D4 SMCJ58A TVS equivalent
    • U7 LMR33630 5V buck
    • U16 AP63300 buck
    • U8/U9/U15 PMEG4030ER Schottky diodes
    • L1/L2 inductors
    • Power capacitors/resistors around the buck regulators
  • Wired much of the input protection and 5V buck section:
    • VCC_IN
    • PWR_GND
    • PROTECTED_12V
    • +5V
    • U7_SW
    • U7_BOOT
    • U7_FB
    • U7_VCC
    • U7_PG
  • Consulted datasheets for the AP63300 and LMR33630 regulator topology before wiring.
Important caveat:
  • Work stopped mid-power-block. The AP63300 / 12V distribution section is not fully wired or validated yet.
  • I also added four 10uF capacitors intended as C14-C17, but because of existing designator conflicts they were assigned as C14, C9, C10, and C11. These need to be renamed/fixed when ACUs are available.
Current state:
  • The schematic is partially reconstructed.
  • Do not proceed to layout yet.
  • Next step is to finish wiring and validating the power block, then continue block-by-block: Pi Zero header, W5500 Ethernet, RS-485 muxed OSDP, MCP23017 I/O, opto inputs, and relays.
Fix power block
Run ERC review
AP63300 wiring gaps
Pi header next
GND
R15 P2 - C5 P2
R15 P2 - C5 P2
GND
GND
GND
R15 P2 - C5 P2
GND
GND
R15 P2 - C5 P2
R15 P2 - C5 P2
GND
GND
F1 P2 - D4 1
F1 P2 - D4 1
L1 2 - C5 P1
L1 2 - C5 P1
U7 BOOT - C4 P1
U10 2 - D4 2
U7 FB - R12 P2
U7 PG - R10 P2
U7 BOOT - C4 P1
U10 1 - F1 P1
U10 1 - F1 P1
F1 P2 - D4 1
L1 2 - C5 P1
U7 VCC - C3 P1
U7 PG - R10 P2
F1 P2 - D4 1
L1 2 - C5 P1
L1 2 - C5 P1
L1 2 - C5 P1
F1 P2 - D4 1
U7 FB - R12 P2
U7 FB - R12 P2
U10 2 - D4 2
F1 P2 - D4 1
U7 SW - L1 1
F1 P2 - D4 1
L1 2 - C5 P1
U10 2 - D4 2
U7 SW - L1 1
U7 SW - L1 1
U7 VCC - C3 P1
F1 P2 - D4 1
F1 P2 - D4 1
R15
Resistance
24.9kΩ
R42
Resistance
100kΩ
C3
Capacitance
1uF
C7
Capacitance
22uF
C20
Capacitance
100nF
C11
Capacitance
10uF
C6
Capacitance
22uF
R40
Resistance
10kΩ
C2
Capacitance
220nF
R25
Resistance
140kΩ
C8
Capacitance
22uF
C4
Capacitance
100nF
R24
Resistance
0 Ω
C9
Capacitance
10uF
R12
Resistance
100kΩ
C18
Capacitance
10uF
C5
Capacitance
22uF
C19
Capacitance
47pF
C10
Capacitance
10uF
F1
C1
Capacitance
10uF
R10
Resistance
100kΩ
C14
Capacitance
10uF
U6
Resistance
43.2kΩ
D4
Not Recommended for New Designs
U7
L2
U9
U15
L1
U16
U8
U10

Refine this doc
Ask about this doc
CM4 GPIO Migration Map
Source Design Reviewed
Uploaded files reviewed:
  • Schematic_PI-ZERO-2W-METERUM-ZERO-DOOR_2026-05-25 PDF
  • BOM CSV, pick-and-place CSV, Gerber ZIP were queried, but the searchable extraction did not return usable rows for the GPIO mapping. The schematic PDF extraction was usable and is the basis for this map.
Correction after user review: the Gerber ZIP, BOM CSV, and pick-and-place CSV were not actually extractable by the available file reader in this session; all direct re-query attempts returned no usable manufacturing-file data. The earlier schematic rewrite attempt was therefore premature and has been rolled back to avoid building from an incomplete interpretation.
Current Flux project state after rollback: empty schematic, 0 components, 0 nets.
Existing Pi Zero 2W Functions Found
The original design uses a Raspberry Pi Zero 2W 40-pin header footprint/net block, marked as PI2 / U5 in the source schematic.
Power and Common Nets

Table

Existing netPi Zero header functionCM4 carrier action
+5V / 5VPi header pins 2 and 4Feed CM4 +5V input pins through the carrier-board 5 V rail. Recalculate 5 V rail current because CM4 can draw materially more than Pi Zero 2W.
3V3Pi header pins 1 and 17Do not back-feed CM4 3V3 unless following CM4 carrier design rules. Treat 3V3 as local carrier I/O rail generated/available per CM4 design.
GNDPi header ground pinsTie CM4 grounds to board ground with solid return paths.
GPIO / Peripheral Mapping
The CM4 exposes the same BCM GPIO numbering for the standard low-speed GPIO functions. For this design, the intended migration is to keep the same BCM GPIO assignments wherever possible so existing Linux/software pin references remain mostly unchanged.

Table

Function in existing designExisting Pi Zero netPi Zero BCM GPIO / header pinCM4 migration targetNotes
I2C SDA for MCP23017SDA / SDA_GP2GPIO2 / pin 3CM4 GPIO2 / I2C1 SDAAlso connects to MCP23017 SDA. Keep 4.7 k pull-up to 3V3 if not already provided elsewhere.
I2C SCL for MCP23017SCL / SCL_GP3GPIO3 / pin 5CM4 GPIO3 / I2C1 SCLAlso connects to MCP23017 SCK/SCL. Keep 4.7 k pull-up to 3V3.
RS-485 TX to MAX3485 DIUART_TX / TXO_GP14GPIO14 / pin 8CM4 GPIO14 / UART0 TXD3.3 V UART logic is compatible with MAX3485 VCC=3V3.
RS-485 RX from MAX3485 ROUART_RX / RXI_GP15GPIO15 / pin 10CM4 GPIO15 / UART0 RXD3.3 V UART logic.
RS-485 driver/receiver enableRS485_DE_REGPIO17 / pin 11CM4 GPIO17Drives MAX3485 DE and RE#. Ensure polarity matches firmware: DE high enables driver, RE# low enables receiver.
TMUX address bit 0MUX_A0Likely GPIO23 or GPIO24 from Pi header blockCM4 same BCM GPIO once confirmedOCR shows MUX_A0 connected to Pi block but not a reliable header pin. Needs source CAD/netlist confirmation.
TMUX address bit 1MUX_A1Likely GPIO23 or GPIO24 from Pi header blockCM4 same BCM GPIO once confirmedOCR shows MUX_A1 connected to Pi block but not a reliable header pin. Needs source CAD/netlist confirmation.
TMUX enableMUX_ENLikely GPIO22 or GPIO27 from Pi header blockCM4 same BCM GPIO once confirmedTMUX1309 EN# is active-low; firmware polarity must be confirmed.
Ethernet Migration Decision
Decision: switch from the W5500 SPI Ethernet controller to the CM4 native Ethernet interface, assuming the product still only needs one wired Ethernet port.
Why this is preferred
  • Removes the W5500 IC and its support components: 25 MHz crystal/load capacitors, SPI series/strap components, local decoupling, reset/interrupt wiring, and SPI chip-select/control nets.
  • Frees Pi/CM4 GPIO8, GPIO9, GPIO10, GPIO11, and the W5500 interrupt/reset GPIOs for other uses or future expansion.
  • Reduces BOM cost and assembly complexity by avoiding a separate Ethernet controller IC.
  • Simplifies Linux software: use CM4's native Ethernet MAC/PHY path instead of configuring an SPI Ethernet overlay/driver.
  • Improves performance headroom versus SPI Ethernet.
What remains required
  • Keep an Ethernet magnetics/RJ45 solution compatible with the CM4 native Ethernet interface. Important correction: the earlier HR911105A part is a 10/100 MagJack and is not sufficient for CM4 native Gigabit Ethernet; use a 1000Base-T MagJack or intentionally limit the design only if acceptable.
  • Route native Ethernet differential pairs with controlled impedance and continuous ground reference.
  • Use a 4-layer PCB minimum for reliable native Ethernet routing: top signal, solid GND plane, power plane, bottom signal.
  • Place the RJ45/magnetics close to the CM4 Ethernet pins and avoid stubs, plane splits, or noisy power switching areas under the pairs.
Removed GPIO mappings
The following old Pi Zero assignments are no longer needed if W5500 is removed:

Table

Removed functionExisting netOld Pi Zero GPIOResult after native Ethernet migration
W5500 SPI chip-selectSCSn / CE0_GP8GPIO8Freed
W5500 SPI clockSCLK / SCLK_GP11GPIO11Freed
W5500 SPI MOSIMOSI / MOSI_GP10GPIO10Freed
W5500 SPI MISOMISO / MISO_GP9GPIO9Freed
W5500 interruptINTnlikely GPIO25Freed / no longer required
W5500 resetnRSTunclearFreed / no longer required for Ethernet
Other Functional Blocks Identified
  • TMUX1309APWR multiplexes RS-485 A/B paths across four OSDP ports.
  • MAX3485AEASA+T is the 3.3 V RS-485 transceiver.
  • MCP23017-E/SS handles door/REX inputs and relay outputs over I2C.
  • Original W5500 SPI Ethernet block should be removed and replaced with the CM4 native Ethernet RJ45/magnetics implementation.
  • Power tree includes protected 12 V input, 12 V-to-5 V regulator, and 3.3 V rails.
CM4 Migration Design Direction
  1. Replace the Pi Zero 2W 40-pin module/header with a CM4 module interface using the standard CM4 board-to-board connectors.
  2. Preserve BCM GPIO assignments for low-speed functions wherever possible:
    • GPIO2/3 for I2C
    • GPIO14/15 for UART0 RS-485
    • GPIO17 for RS-485 DE/RE
  3. Remove the W5500 SPI Ethernet block and use CM4 native Ethernet instead.
  4. Confirm exact GPIOs for MUX_A0, MUX_A1, and MUX_EN from the source CAD/netlist before committing the final schematic. INTn and W5500 nRST are no longer blockers if native Ethernet replaces W5500.
  5. Rework power for CM4 current demand. The previous 5 V rail may be undersized for CM4 plus relays and peripherals.
  6. Add CM4-required support circuits per the official CM4 carrier-board design guidance: connectors, boot/eMMC selection as needed, USB if required, native Ethernet magnetics/RJ45, HDMI/camera/display only if used, antenna keepout if using wireless CM4.
Open Questions Before Schematic Rewrite
  1. Which CM4 variant should be used: wireless or non-wireless, eMMC size, RAM size?
  2. Does this board need CM4 USB access for programming/service, or only Ethernet/network access?
  3. Are HDMI, CSI camera, DSI display, PCIe, or USB host required?
  4. Can the original source CAD/netlist be provided to confirm ambiguous GPIOs that the PDF OCR could not resolve? The remaining critical ambiguous nets are MUX_A0, MUX_A1, and MUX_EN.
  5. Please provide the original editable EDA source or a full schematic/netlist export if possible. The current attachments are not enough for a faithful rewrite because the Gerber/BOM/PnP content could not be extracted here.

  • Source Design Reviewed

  • Existing Pi Zero 2W Functions Found

  • Power and Common Nets

  • GPIO / Peripheral Mapping

  • Ethernet Migration Decision

  • Why this is preferred

  • What remains required

  • Removed GPIO mappings

  • Other Functional Blocks Identified

  • CM4 Migration Design Direction

  • Open Questions Before Schematic Rewrite

Documents

Assets

No assets added.

Stupid Amber Massive Robot Spider

Stupid Amber Massive Robot Spider thumbnail
Migration of the Pi Zero 2W Meterum Zero Door controller design to a Raspberry Pi Compute Module 4 carrier while preserving existing GPIO functions.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$2.31–$3.01

Digi-Key

$2.59

HQonline

$1.97

LCSC

$2.16–$3.20

Mouser

$6.93–$7.51

TME

$7.25

Verical

$2.09–$7.61

Controls