RTL8761BTV Breakout Board

Worked for 6 mins 16 sec

flux

I’m blocked again because your account has no available ACUs, so the cleanup autoroute paused before finishing.

Accomplished this session:

Applied the intended Standard 4 Layer stackup correctly.
Completed one autoroute pass earlier: 462 route nodes were added.
Fixed the stackup mismatch that caused 45 invalid-layer DRC errors.
Rechecked the board: routing congestion is now reported as acceptable.

Remaining work:

Cleanup autoroute is paused due to missing ACUs.
Final DRC still had 6 airwires before the cleanup pass:
- GND/thermal-pad related connection
- LED_LOG
- BT_UART_CTS_IC
- DIS_BT_N
- BT_UART_RTS_IC
The paused cleanup run also reported a placement/preflight anomaly and a decoupling-rule routing warning that should be reviewed after ACUs are available.

Suggested next steps:

Add ACUs, then resume the paused cleanup autoroute.
Re-run final airwire/DRC checks.
Manually inspect the RF path, QFN fanout, ground/thermal pad, and crystal routing before manufacturing.

Resume and inspect

Locate airwires

Review placement anomaly

Check RF routing

Manufacturing DRC report

R1 P2 - J1 Pin_3

U1 GPIOA11_DIS_BT_N - R12 P1

U1 GPIOA23_LED_LOG - R14 P1

R4 P2 - J1 Pin_6

U1 XO - Y1 HOT_2

U1 BT_VD12SYN - C3 P1

U1 GPIOA13_HOST_WAKE_BT - J2 Pin_3

U1 BT_VD33PA - C1 P1

U1 GPIOB0_RT_SDA - J2 Pin_8

U1 REG_OUT - L1 1

R2 P2 - J1 Pin_4

U1 BT_RFIO - C17 1

U1 BT_VD12SYN - C3 P1

U1 BT_VD33PA - C1 P1

U1 BT_VD12SYN - C3 P1

C17 2 - L2 1

J1 Pin_1 - J2 Pin_1

U1 GPIOA5_UART_RTS_32K_IN - R3 P1

U1 BT_VD12SYN - C3 P1

U1 GPIOA0_PCM_IN_ICFG0 - R5 P1

U1 GPIOA9_BT_ACT_SPS_LDO_SEL - R10 P1

U1 GPIOA14_BT_WAKE_HOST_EEPROM_SEL - R11 P1

U1 REG_OUT - L1 1

J1 Pin_1 - J2 Pin_1

U1 BT_VD33PA - C1 P1

L2 2 - J3 1

U1 BT_VD12SYN - C3 P1

U1 GPIOA3_PCM_CLOCK_ICFG3 - R8 P1

J1 Pin_1 - J2 Pin_1

R1 P2 - J1 Pin_3

U1 GPIOB1_RT_SCL - J2 Pin_7

R2 P2 - J1 Pin_4

U1 GPIOA0_PCM_IN_ICFG0 - R5 P1

C17 2 - L2 1

R3 P2 - J1 Pin_5

U1 GPIOA1_PCM_OUT_ICFG1 - R6 P1

U1 GPIOA4_UART_CTS - R4 P1

U1 GPIOA1_PCM_OUT_ICFG1 - R6 P1

U1 GPIOA9_BT_ACT_SPS_LDO_SEL - R10 P1

U1 GPIOB0_RT_SDA - J2 Pin_8

U1 XI - Y1 HOT_1

U1 XO - Y1 HOT_2

U1 GPIOA2_PCM_SYNC_ICFG2 - R7 P1

L2 2 - J3 1

U1 GPIOA14_BT_WAKE_HOST_EEPROM_SEL - R11 P1

U1 GPIOB2_RT_INT - J2 Pin_6

U1 GPIOA15_CLK_REQ - R13 P1

U1 GPIOA7_UART_IN - R2 P1

U1 GPIOA11_DIS_BT_N - R12 P1

U1 GPIOB2_RT_INT - J2 Pin_6

U1 BT_RFIO - C17 1

U1 GPIOA23_LED_LOG - R14 P1

U1 BT_VD12SYN - C3 P1

U1 GPIOA4_UART_CTS - R4 P1

U1 BT_VD12SYN - C3 P1

U1 GPIOA15_CLK_REQ - R13 P1

C17 2 - L2 1

U1 XI - Y1 HOT_1

R3 P2 - J1 Pin_5

U1 GPIOA14_BT_WAKE_HOST_EEPROM_SEL - R11 P1

U1 BT_VD12SYN - C3 P1

U1 GPIOA13_HOST_WAKE_BT - J2 Pin_3

U1 GPIOA5_UART_RTS_32K_IN - R3 P1

U1 XI - Y1 HOT_1

U1 GPIOA2_PCM_SYNC_ICFG2 - R7 P1

U1 GPIOA15_CLK_REQ - R13 P1

U1 BT_VD33PA - C1 P1

R4 P2 - J1 Pin_6

U1 GPIOA8_BT_STE_TEST_MODE_SEL - R9 P1

U1 GPIOA6_UART_OUT - R1 P1

U1 GPIOA11_DIS_BT_N - R12 P1

L1 2 - U1 VDD12BT

U1 BT_VD33PA - C1 P1

U1 XO - Y1 HOT_2

U1 BT_VD33PA - C1 P1

U1 BT_RFIO - C17 1

U1 GPIOA8_BT_STE_TEST_MODE_SEL - R9 P1

U1 GPIOB1_RT_SCL - J2 Pin_7

U1 GPIOA3_PCM_CLOCK_ICFG3 - R8 P1

U1 GPIOA6_UART_OUT - R1 P1

U1 GPIOA23_LED_LOG - R14 P1

U1 GPIOA7_UART_IN - R2 P1

L1 2 - U1 VDD12BT

U1 BT_VD33PA - C1 P1

C14

Capacitance

12pF

R10

Resistance

10kΩ

Resistance

10kΩ

R11

Resistance

10kΩ

Resistance

33Ω

Capacitance

100nF

Resistance

33Ω

Capacitance

100nF

Capacitance

1uF

Resistance

10kΩ

Capacitance

10uF

R13

Resistance

10kΩ

Capacitance

1uF

C13

Capacitance

12pF

Resistance

10kΩ

Capacitance

4.7uF

Resistance

10kΩ

C16

Capacitance

1.2pF

R12

Resistance

10kΩ

C18

Capacitance

2pF

Resistance

33Ω

C15

Capacitance

1.2pF

Capacitance

1uF

Resistance

33Ω

Resistance

10kΩ

C10

Capacitance

100nF

C12

Capacitance

100nF

C11

Capacitance

100nF

Capacitance

100nF

R14

Resistance

10kΩ

Capacitance

1uF

J3 2 - C15 P2

Inductance

2.7nH

J3 2 - C15 P2

Inductance

2.2uH

J3 2 - C15 P2

C8 P2 - J1 Pin_2

GND

J3 2 - C15 P2

C8 P2 - J1 Pin_2

J3 2 - C15 P2

J3 3 - C1 P2

C8 P2 - J1 Pin_2

J3 2 - C15 P2

C8 P2 - J1 Pin_2

J3 2 - C15 P2

C8 P2 - J1 Pin_2

J3 2 - C15 P2

C8 P2 - J1 Pin_2

J3 2 - C15 P2

C8 P2 - J1 Pin_2

J3 2 - C15 P2

C17

Capacitance

22pF

J3 2 - C15 P2

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Project Specification — RTL8761BTV UART Breakout

Project Overview

Status: Draft schematic.

Prototype breakout board for the Realtek RTL8761BTV-CG Bluetooth 5 controller in QFN-32, 4 x 4 mm, 0.4 mm pitch package. The board is intended for UART HCI firmware bring-up and breadboard development.

Intended Use

Lab/prototype bring-up of RTL8761BTV-CG over UART HCI.
Breadboard or jumper-wire connection to a 3.3 V host UART.
Not production-certification-ready; RF tuning and regulatory validation remain open.

What the Device Should Do

Power the RTL8761BTV-CG from an external 3.3 V rail.
Generate the chip's 1.26 V core/RF rail using the internal regulator in SPS mode.
Break out UART TX/RX/RTS/CTS to 0.1 inch headers.
Provide default boot strap states for normal UART HCI operation.
Provide 40 MHz clock, RF matching, and antenna/measurement provisions.

Main Features

RTL8761BTV-CG Bluetooth 5 UART HCI controller.
0.1 inch power/UART header: 3V3, GND, host TX/RX, RTS/CTS.
3.3 V and 1.26 V decoupling network.
2.2 uH SPS inductor from REG_OUT/LX_CORE to 1.26 V rail.
40 MHz crystal with C0G load capacitors.
RFIO pi matching and DC-blocking network for a 2.4 GHz antenna path.
Default 10 kΩ strap resistors for normal boot.

System Architecture

Diagram

Hardware Subsystems

Power: external regulated 3.3 V input; on-chip regulator support for 1.26 V rail.
Bluetooth controller: Realtek RTL8761BTV-CG, UART HCI variant.
Host interface: UART_IN, UART_OUT, UART_CTS, UART_RTS on breadboard-compatible header.
Clock: 40 MHz crystal on XI/XO.
RF: 2.4 GHz RFIO matching path with placeholder/tunable values from public reference notes.
Boot/control: strap pins biased for normal operation and exposed where useful.

Interfaces and Connections

3V3 input: external regulated 3.0–3.63 V supply; board assumes 3.3 V nominal.
UART logic: defaults to VIO_UART = 3.3 V. Not 5 V tolerant.
RF: 50 ohm layout required during PCB layout.

Power Tree and Power Budget

Table

Rail	Source	Loads	Design note
3V3	External header	REG_IN, VIO_SB, VIO_UART, VDDIO33, BT_VD33PA	Host/source should support at least 250 mA for bring-up margin.
1V26	RTL8761BTV internal regulator via 2.2 uH inductor	VDD12BT, BT_VD12RTXBB, BT_VD12RTXFE, BT_VD12SYN	Datasheet/regulator table indicates 1.26 V typ, 2.2 uH, 4.7 uF output cap.

Firmware-Relevant Hardware Requirements

Host should use RTL8761B UART HCI firmware/config flow, typically Realtek rtl8761b_fw and rtl8761b_config on Linux.
Initial UART bring-up may require hardware flow control and 115200 baud before firmware/baud changes.
Header labels should use host perspective and RTL perspective to avoid TX/RX confusion.

Physical Design Expectations

Breadboard-friendly 0.1 inch headers.
QFN-32 requires assembly, not beginner hand-soldering.
RF section needs short 50 ohm controlled-impedance routing and antenna keepout.
Exposed pad must be tied to ground with vias.

Important Design Decisions

Use exact RTL8761BTV-CG custom library part created from public LCSC/Realtek pinout data.
Use SPS mode by default: SPS_LDO_SEL pulled low and 2.2 uH inductor fitted.
Use 3.3 V UART by default; VIO_UART is tied to 3V3 in this revision.
Use 10 kΩ weak strap resistors for normal boot.

Assumptions and Risks

Public RTL8761B datasheet/reference snippets are sufficient for Rev A prototype, but Realtek HDK details may refine RF/strap values.
RF matching values are starting values and should be tuned on the final layout/antenna.
5 V UART hosts require level shifting; this board is 3.3 V only unless revised.

Change Notes

Initial schematic design started from user request on 2026-07-16.

Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power Tree and Power Budget
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions and Risks
Change Notes

Reviews

Documents

Project Specification — RTL8761BTV UART Breakout

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Assets are files uploaded to this project which can be used in various ways.

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