ESP32 LED Board Design
Worked for 6 mins 5 sec
Created 4 project docs
Block Diagram
Block Diagram
System Architecture
Assemblies
- Main controller/power PCB — USB-C PD input, 2S charger/protection/balancing, 5 V LED buck, 3.3 V MCU buck, ESP32-C3, level shifting, LED output, pack connector, debug/programming, and button-cable connector.
- Separate six-button PCB — six momentary switches and matching polarized locking ribbon connector. Allocation: six signals, two grounds, and two reserved/ground positions for return-path robustness.
- USB-C PD sink: reference search required; import exact/close standalone reference if available.
- Balanced 2S charger: reference search required; import exact/close standalone reference if available.
- 2S protection/balancing: reference search required; import exact/close standalone...
Project Specification
Project Specification
Project Overview
Status: Draft — schematic phase. A two-PCB BLE LED controller for installation in a non-conductive tube.
Intended Use
Portable battery-powered controller for 100 Adafruit ADA2328 5 V addressable LEDs, operated by six wired buttons and BLE.
What the Device Should Do
- Drive 100 addressable LEDs while enforcing a 20 W electrical LED-output cap.
- Provide BLE control with Wi-Fi disabled in firmware.
- Charge a protected/balanced 2S 18650 pack from a USB-C PD supply.
- Positively disable LED power and normal operation whenever USB-C is inserted/charging.
- Read six independent momentary buttons on a separate PCB.
ESP32-C3 module; 2S pack protection/balancing; 9 V PD sink; balanced 2S charger; 5 V/4 A LED rail; efficient ...
Firmware Getting Started
Firmware Getting Started
Toolchain
PlatformIO + Arduino-ESP32.
Final MCU Pin Mapping
Compilable Starter (platformio.ini:src/main.cpp)
Startup SequenceDepending on Arduino-ESP32 release, include `` and omitbtStop()if it conflicts with NimBLE startup. The hardware shutdown/charge inhibit must not depend on this firmware.
- Confirm hardware charge inhibit is inactive.
- Initialize serial diagnostics.
- Keep Wi-Fi disabled.
- Configure buttons and ADC.
- Initialize FastLED power limiter before enabling patterns.
- Start BLE GATT service and advertising.
Board Bring-Up Plan
Board Bring-Up Plan
Preconditions
Do not install cells until charger, protection, and regulator support circuits have been checked against final datasheets and ERC is clean. Use a current-limited bench supply and thermal camera.
Main Board
- Visual inspection: polarity, exposed pads, solder bridges, antenna keepout, connector pin-1 orientation.
- Resistance checks: GND-to-pack, GND-to-5 V, and GND-to-3.3 V must not be shorted.
- Power protected pack input from 6.0 V at 100 mA limit with LED load disconnected. Pass: no unexpected heating/current-limit entry.
- Verify 3.3 V rail within ±3%; verify EN reset behavior and programming access.
- Verify ESP32 boot log; flash starter firmware; confirm BLE advertising with Wi-Fi disabled.
The specification and six-button subsystem are complete. I found the first pass left the high-power charging and protection circuitry unfinished, so I’m completing that block now rather than treating an unsafe partial schematic as done.
Worked for 12 mins 19 sec
The requirements, power budget, firmware starter, bring-up plan, six-button board, and most main-controller circuitry are complete. The design now includes full 2S protection, USB-C PD charging, charge-time shutdown, 5 V/4 A LED power, and ESP32-C3 BLE control.
Blocked: a manufacturable 3-wire battery connector must be selected for PACK− / cell midpoint / PACK+, followed by a final capacitor/package audit and ERC cleanup. Please specify a preferred connector family—JST-XH, JST-PH, or direct solder pads—before I finalize the schematic.
Use JST-XH connector
Use JST-PH connector
Use solder pads
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Project Specification
Project Overview
Status: Draft — schematic phase. A two-PCB BLE LED controller for installation in a non-conductive tube.
Intended Use
Portable battery-powered controller for 100 Adafruit ADA2328 5 V addressable LEDs, operated by six wired buttons and BLE.
What the Device Should Do
- Drive 100 addressable LEDs while enforcing a 20 W electrical LED-output cap.
- Provide BLE control with Wi-Fi disabled in firmware.
- Charge a protected/balanced 2S 18650 pack from a USB-C PD supply.
- Positively disable LED power and normal operation whenever USB-C is inserted/charging.
- Read six independent momentary buttons on a separate PCB.
Main Features
ESP32-C3 module; 2S pack protection/balancing; 9 V PD sink; balanced 2S charger; 5 V/4 A LED rail; efficient 3.3 V rail; battery ADC; debug/programming; high-current LED connector; locking polarized button ribbon cable.
System Architecture
See the dedicated Block Diagram file. Two electrically connected assemblies share six button signals and multiple ground returns.
Hardware Subsystems
- Battery: two series 3000–3500 mAh 18650 cells, 7.4 V nominal, 8.4 V full; design minimum 6.0 V before protection cutoff.
- Charging: USB-C PD sink requests 9 V; balanced 2S charger set conservatively to 1.0 A.
- Safety: cell-level 2S over/under-voltage and over-current protection plus balancing; charging presence/state hard-disables normal and LED power paths.
- LED power: synchronous buck, 6.0–8.4 V input, 5 V/4 A continuous output, current/fuse protection and bulk capacitance.
- Logic: efficient 3.3 V regulator sized for ESP32-C3 BLE peaks; 5 V logic buffer for LED data.
- User interface: six active-low buttons, main-board pull-ups, cable series resistors/ESD, firmware debounce.
Interfaces and Connections
USB-C power input; 2S battery/cell-tap connector; 5 V/GND/data LED connector(s); 10-position polarized locking ribbon connector between boards; programming/debug header.
Power and Runtime Expectations
LED output is capped at 20 W. Typical cell assumption is 3.0–3.5 Ah. Continuous full-cap output is thermally demanding inside a tube and is not expected to guarantee one hour for all cell capacities.
Power Tree and Power Budget
Assumptions: 5 V buck efficiency 90% worst-case budget; 3.3 V buck 90%; ESP32-C3/control 0.50 W peak allocation; usable battery energy approximately 80% of nominal due to cutoff, conversion, cell aging, and high-current discharge.
Table
| Load / source | Output | Input-equivalent at 6.0 V |
|---|---|---|
| LEDs (hard cap) | 5 V × 4 A = 20.0 W | 20/0.90/6.0 = 3.70 A |
| ESP32-C3 + buffer/control peak allowance | 0.50 W | 0.50/0.90/6.0 = 0.093 A |
| Protection/control margin | 0.25 W | 0.042 A |
| Worst-case pack peak | 22.97 W | 3.83 A |
Power-path parts, pack connector, protection FETs, and wiring shall support at least 5 A continuous design current with transient margin; 5 V converter is rated above 4 A and its inductor saturation current must exceed worst-case peak inductor current.
Nominal pack energy: 7.4 V × 3.0–3.5 Ah = 22.2–25.9 Wh. At 80% usable: 17.8–20.7 Wh. At about 22.5–23 W battery demand, estimated full-cap runtime is about 0.77–0.92 h; therefore the one-hour target is not guaranteed at the 20 W cap. Firmware brightness limiting and typical animations should extend runtime; a true one-hour worst-case target requires larger cells, reduced LED cap, or parallel capacity.
Charging at 1.0 A reaches 8.4 W battery charge power. At 90% charger efficiency, 9 V input is about 1.04 A; specify a 9 V PD supply rated at least 2 A for cable, thermal, and transient margin. Approximate ideal charge time is 3.0–3.5 h plus CV taper.
Manufacturing and Assembly Expectations
Compact SMD design, narrow main PCB for a 2-inch-ID tube. High-current and switch-mode layout require short loops, adequate copper, thermal vias/pours, and separation from antenna keepout.
Firmware-Relevant Hardware Requirements
BLE only; Wi-Fi disabled. Avoid ESP32-C3 strapping and native USB pins for buttons and LED output. Firmware enforces aggregate brightness/power, debounces buttons, monitors battery voltage, and remains inactive while charging.
Physical Design Expectations
Maximum usable axial envelope 12 inches. Main PCB must be narrower than the tube ID with mechanical clearance. ESP32 module antenna remains inside ordinary plastic tube with an air gap; no copper, traces, wires, screws, bosses, cells, or other hardware in the antenna region.
Important Design Decisions
- 2S architecture with 9 V USB-C PD charging.
- 1.0 A conservative charge rate for thermal practicality and typical 3000–3500 mAh cells (~0.29–0.33 C).
- Hardware charge-present/state inhibit, not firmware-only shutdown.
- Ten-way locking polarized ribbon allocation for six signals plus robust grounds/spares.
Assumptions
Cells are matched, quality protected-pack-grade 18650s with discharge capability above 5 A. Tube is non-conductive plastic. ADA2328 data protocol is treated as WS2812-class 800 kHz single-wire signaling; final strip connector pin order must be checked against the actual purchased strip.
Change Notes
Initial schematic requirements and pre-selection power budget captured.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes
