Schematic Design Review

flux

The dialog is blocking the UI export because 12 generic resistors/capacitors have no Manufacturer Part Number (MPN):
R1, R2, R5, C1, C2, C3, C5, C6, C7, C8, VS1, VS2
The PCB geometry itself is exportable—the direct Gerber exporter succeeded and the archive is valid. The UI’s manufacturing gate also treats missing sourcing data as an error, even though MPNs are not required to fabricate a bare PCB.
  • Bare PCB only: select Export with errors; the Gerbers are valid.
  • PCB assembly: assign real MPNs to those 12 generic parts before exporting the BOM/placement files.
My earlier check excluded the MPN manufacturing review, which is why I incorrectly said there were no blockers.
I

irflashrex

well fix the MPN's then.

flux

I’ll source exact purchasable resistor and capacitor MPNs matching each existing value, voltage rating, dielectric, and footprint, assign them without changing the PCB geometry, then rerun the manufacturing review.

flux

All 12 generic passives now have verified MPNs matching their existing footprints and electrical ratings. I’m rerunning the same manufacturing gate that blocked the export, plus the PCB checks.

flux

The manufacturing metadata is updated; the final review is checking for any remaining blockers.

flux

Fixed all 12 missing MPNs with footprint- and rating-compatible Yageo/Murata parts.
The manufacturing review now reports no errors, warnings, or open blockers. Close and reopen the export dialog if it is still showing the cached warning.
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Files

Schematic

Layout

3D View

USB-C Power Upgrade
Outcome
USB-C electrical/PCB replacement batch completed. The board is not globally ERC/manufacturing-clean because unrelated pre-existing findings remain. No outline, stackup, or unrelated component-placement changes were made.
Scope status

Table

Assigned itemStatusEvidence/result
1. Inspect existing connector, schematic and routingCompletedMolex 1050170001 usb power had VBUS on 5vdc, ground and six shield terminals on GND, and floating D−/D+/ID. Baseline routing had 0 airwires and 0 redundant traces.
2. Select real library USB-C receptacleCompletedGCT USB4105-GF-A, retained designator usb power; library footprint has paired power/ground lands, independent CC pads, four plated slotted shell stakes, two locating holes and a STEP model. Manufacturer pin table verified. Library footprint/edge geometry and installed 3D orientation inspected. See verification limits below.
3. Replace connector and preserve netsCompletedRemoved Molex connector and added GCT connector in one component mutation, explicitly reconnected existing 5vdc and GND. Old D−/D+/ID pins had no nets to remove. No legacy data connections remain.
4. Add independent Rd resistorsCompletedR3 = CC1, R4 = CC2; each 5.1 kΩ, 1%, validated SMD_0402_1005Metric, Role=Pull-Down, descriptive CC-specific Role Details. Sourced MPN RC0402FR-075K1L, Yageo, LCSC C105872.
5. Unused signal handlingCompletedSix explicit NC markers: DP1/A6, DN1/A7, DP2/B6, DN2/B7, SBU1/A8, SBU2/B8. No SuperSpeed or ID terminals in this USB 2.0 footprint. CC nets remain separate.
6. Schematic power-input blockCompletedNew parts share Functional Group USB-C Power Input; automatically positioned block inspected in schematic image and exact netlist. Connections use named rail/CC stubs. No new schematic-legibility errors/warnings reported. Manual arrangement tool was not exposed in this session; no claim of manual repositioning is made.
7. PCB edge placementCompletedTop-side connector at (-15.00, +15.85) mm, rotation 180°, mouth toward +Y board edge y=18.50 mm. R3 at (-13.75, +9.20) mm and R4 at (-16.75, +9.20) mm, both top, 270°. Edge-rule readback faces up; 3D front/isometric views show an unobstructed outward opening. No body overlap, keepout or out-of-bounds errors.
8. Copper replacement/routingCompletedDeleted six stale Micro-USB VBUS traces. Added two 0.3 mm VBUS escape traces, two 0.6/0.3 mm through vias, a 0.5 mm bottom power bridge and 0.5 mm feed to existing regulator input. CC routes are independent 0.15 mm traces, about 1.35 mm each. Ground/shield pads and resistor returns connect to existing GND fill. Two zero-length router artifacts were deleted. No differential breakout.
9. ERC/DRC and remediationCompletedAll introduced electrical, copper and placement errors fixed. Final routing: 0 airwires, 0 redundant traces. Board routing-feasibility check valid, with no anomalies. Detailed remaining counts below.
Verified pin mapping
Manufacturer A-side table assigns A5=CC1, A6=Dp1, A7=Dn1, A8=SBU1; A4/A9 are VBUS and A1/A12/shell are ground.
Manufacturer B-side table assigns B5=CC2, B6=Dp2, B7=Dn2, B8=SBU2; B4/B9 are VBUS and B1/B12/shell are ground.

Table

Installed terminalConnection
VBUS / A4_B9Existing 5vdc
VBUS__1 / B4_A9Existing 5vdc
GND / A1_B12; GND__1 / B1_A12Existing GND
SHELL_GND through SHELL_GND__3 / SH1–SH4Existing GND
CC1 / A5USB_CC1 → R3:P1; R3:P2 → GND
CC2 / B5USB_CC2 → R4:P1; R4:P2 → GND
A6, A7, B6, B7, A8, B8Intentionally NC
The library combines each pair of VBUS contacts into one solder land and each pair of GND contacts into one solder land; both power lands and both ground lands are connected. Connector Part Type was changed from USB C to Connector to remove an erroneous inherited 90 Ω VBUS impedance classification. Final net readback shows no controlled impedance on 5vdc.
Geometry and limits of verification
  • Retained the existing 50 × 37 mm rectangular board and existing custom two-copper-layer stackup, without resizing.
  • Library footprint datum: mouth toward local −Y; required edge offset 2.65 mm. At 180° placement and y=15.85 mm the board edge is y=18.50 mm. Library fabrication outline mouth is nominally y=18.45 mm in this placement.
  • Inspected library lands: signal pads 0.30 × 1.15 mm; paired power/ground pads 0.60 × 1.15 mm; shell stake centers ±4.32 mm and two rows 4.18 mm apart. These are read-back library dimensions, not independently machine-verified manufacturer dimension claims. Datasheet extraction could not reliably verify all numeric drawing callouts; no custom footprint geometry was invented or authored.
  • The default unsuffixed part has 0.95 mm shell stakes according to the manufacturer ordering grid.
  • The pre-existing custom stackup reports an unusually thin approximately 0.13 mm substrate. It was preserved as requested; mechanical rigidity and production stackup suitability require separate review before fabrication.
  • This is a 5 V passive Type-C sink, not USB-PD negotiation or active current-advertisement detection. This edit does not establish entitlement to 1.5 A/3 A, validate the full board's USB current budget, or add ESD/overcurrent protection.
Final validation counts
Final read-only review: 2026-09-21, approximately 11:01 UTC.

Table

Check groupErrorsWarningsInfo
USB-C-related ERC000
Physical/copper DRC000
Silkscreen-only component override notices003
Whole-board ERC400
Placement020
Manufacturing / missing MPN400
Entire returned review823
Explicitly zero: airwires, redundant traces, overlapping/shorting copper, dangling traces, connector body overlaps, connector out-of-bounds/edge/keepout errors, connector floating-pin errors and NC conflicts. Routing-feasibility check: valid, no issues.
Remaining findings, all outside the electrical scope of this replacement:
  • Four pre-existing MAX232 floating pins: R2OUT, T2IN, R2IN, T2OUT. They were not arbitrarily wired or marked NC.
  • Two pre-existing placement warnings: board density and C3 decoupling loop area. Density remains high after adding the larger connector.
  • Four pre-existing missing-MPN errors: C3, C4, R1, R2. New R3/R4 have sourcing metadata.
  • Three informational, not error/warning, notices for deliberate silkscreen-only overrides on usb power, R3 and R4. These hide crowded imported text or position readable 0.8 mm reference labels; they do not change pads or mating geometry. A USB-C 5V board label is placed beside the connector.
Bring-up checks — unattempted on hardware
  1. Unpowered, verify each CC pin measures approximately 5.1 kΩ to GND, with no direct CC1–CC2 short.
  2. Check VBUS-to-GND for an assembly short and confirm all shell stakes are grounded.
  3. Power from a current-limited 5 V USB-C source; test both plug orientations and verify 5vdc and the existing 3.3 V rail.
  4. Verify operating/peak input current against the attached source's available current; inspect regulator temperature.
  5. Confirm cable insertion clearance and mechanical stake soldering on the manufactured stackup.
No manufactured hardware, full independent land-pattern metrology, or USB compliance test was performed.

  • Outcome

  • Scope status

  • Verified pin mapping

  • Geometry and limits of verification

  • Final validation counts

  • Bring-up checks — unattempted on hardware