This section supersedes the historical incomplete PCB handoff below. Selected parts and logical topology are unchanged.

Coordinates are millimeters from board origin; rotations are CCW; both parts remain on Top.

Only D1 changed position in this continuation; F1 and all USB support passives, the connector, and unrelated components retained their starting positions. D1's anode pad center is approximately (−21.5622, 9.4157) mm; the ground stitch center is 1.288 mm away, approximately 0.588 mm beyond the pad edge. Solid ground copper avoids thermal-spoke inductance.

The raw VBUS branch from the nearby USB contact to D1 is approximately 1.91 mm routed centerline length. The second VBUS contact uses a 22.83 mm top-layer route around the connector pad/anchor obstacles to preserve unrelated copper. Its 0.254 mm width on the existing 35 µm copper gives approximately 44 mΩ at room temperature (ρ=1.72×10⁻⁸ Ω·m), or 24 mV drop / 13 mW if carrying the entire provisional 0.533 A load. Main D1→F1 and protected-rail traces remain 0.5 mm. These are DC estimates, not assembled ESD certification.

Fresh requested checks: 0 airwires, 0 F1/D1 or other component overlaps, 0 overlapping-copper/trace findings, 0 redundant traces, 0 dangling traces, 0 out-of-bounds findings, 0 missing-footprint findings, 0 under-connected-via findings. Read-back confirms USB_VBUS_RAW = both USB VBUS pins + F1:P1 + D1:K, while 5vdc = F1:P2 + regulator VIN + C3:P1. There is no logical bypass; copper checks find no short between those nets. Existing power-budget, USB-source and AMS1117-headroom qualifications below still apply; PCB routing completion does not resolve them.

ESP module RX/TX values are specified typical; the module manual leaves maximum cells blank. MAX3232E no-load current is 0.3 mA typical, 1 mA maximum; loaded supply current is not specified in the consulted source. One transmitter is connected; the other is unused. Its 60 mA short-circuit output limit is not an input-current specification and is not substituted for supply current.

Typical TX/no-load total = 170 + 0.3 + 5 = 175.3 mA at USB VBUS. Conservative design allocation = 500 + 21 + 0.66 + 11 = 532.66 mA. The 3.3 V rail allocation is 521.66 mA. This is an engineering envelope, not a datasheet-guaranteed peak; verify radio startup, TX bursts, RS-232 load and inrush on hardware. ESP 500 mA source-capability evidence lookups failed with evidence_location_invalid for two Espressif sources; that number remains explicitly unverified.

LDO input current approximately equals output current plus ground current; do not scale by 3.3/5. PTC hold-current target ≥1.5 × 532.66 mA = 798.99 mA, before ambient derating. A 1 A low-resistance PTC is the candidate class; select exact part only after this budget.

AMS1117 quiescent current is 5/11 mA typical/max; dropout maximum is 1.3 V at 0.8 A. Use that conservative dropout bound rather than assuming a smaller guaranteed value at this load.

At nominal 5 V, typical TX heat including ground current = (5−3.3)×0.1703 + 5×0.005 = 0.315 W. At a conservative 5.5 V input: 0.402 W typical TX, and 1.208 W if the full 521.66 mA allocation were sustained. SOT-223 θJA is nominally 90°C/W and depends strongly on copper area; maximum junction temperature is 125°C. Approximate rises at 90°C/W: 36°C typical, 109°C sustained allocation. Burst allocation is not safe as continuous load without thermal verification. Existing regulator is retained, not thermally certified by this change.

At 4.75 V connector VBUS, only 150 mV remains above 3.3+1.3 V before PTC and copper losses. At a drooping 4.5 V connector, headroom already fails by 100 mV before protection. Low-resistance PTC minimizes additional drop but cannot fix existing LDO dropout. Robust operation over all USB cable/source conditions requires a future lower-dropout regulator or tighter input-source specification.

Independent 5.1 kΩ Rd only identifies a sink; this board has no CC-advertisement measurement or USB enumeration. Do not infer permission for 1.5 A/3 A, or automatic 500 mA entitlement on every default-current USB source. The 532.66 mA allocation exceeds 500 mA by 32.66 mA. A PTC is slow fault protection, not a USB current limiter or negotiator. Use a known suitable 5 V power source; universal default-current compliance remains unresolved without current detection/management. CC current comes from the source CC circuitry, not the VBUS fuse budget.

Initial read-only DRC/ERC review (2026-09-21 23:07 UTC):

Raw VBUS routing at 0.5 mm failed no-path; a 0.3 mm retry was rejected by the transaction's airwire checks. Stop repeated retries: next engineer should inspect the connector escape and add a controlled short neckdown/fanout with a width justified for 0.533 A, then route raw VBUS. F1/D1 overlap persisted after two spacing corrections despite apparent 2D separation; inspect footprint/model body bounds before moving again or changing rules. Do not fabricate this partial layout: USB input is physically disconnected until those two airwires are completed.

Add resettable series protection and connector-side unidirectional transient suppression while preserving existing CC, no-connect pins, regulator and unrelated routing. Raw-side TVS is for ESD/transients, not sustained overvoltage; a raw-side TVS short is upstream of this PTC and relies on source current limiting. No PD, sustained-overvoltage disconnect, reverse-current blocking or thermal redesign is implied.