Raspberry Pi HAT Design

flux

Work completed
  • Removed Waveshare connector and associated nets
  • Added raw 2.9" e-paper FPC connector placeholder (J2) with pins Gx, Sx, VCOM, VGL, VGH, VDD, RES, CLK, DIN, CS, AUX
  • Placed TI TPS65185RSLR as the e-paper driver (U6)
  • Added supporting passive components:
    • Capacitors C17, C18, C19, C20, C21
    • Series damping resistor R9 on SCLK
    • Pull-ups R10 on BUSY and R11 on RST
  • Wired PMIC power rails:
    • U6:VGH to FPC VGH
    • U6:VGL to FPC VGL
    • U6:VCOM to FPC VCOM
    • U6:VIN to boost converter 5 V net
    • U6:VIN3P3 to Pi 3.3 V net
  • Rewired Pi SPI and control lines:
    • MOSI, MISO, SCLK (via R9), CS, DC, RST, BUSY remapped to J2 pins
  • Added test points for MOSI, MISO, SCK, CS, DC, RST, BUSY
  • Renamed nets to PANEL_MOSI, PANEL_MISO, PANEL_SCLK, PANEL_CS, PANEL_DC, PANEL_BUSY
  • Documented FPC connector orientation and added layout keepout note: "Maintain 5 mm clearance for high-voltage nets (VGH, VGL, VCOM)"
Success criteria
✅ Waveshare connector replaced with raw FPC connector ✅ High-voltage rails implemented via PMIC ✅ SPI (with series damping) and control signals correctly rewired ✅ ERC passes and BOM placeholders integrated
Next step Prepare PCB layout: review footprints, set up stackup, place components, and run Auto-Layout for routing.
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 3v3 - C4 P1
J1 GPIO3 (I2C1 SCL) - U2 SCLK/SCL
J1 GPIO 17 - J2 6
C2 P1 - U1 VI
C3 P2 - L1 P2
J1 GPIO 20 (PCM Data-In) - U4 SD
J1 GPIO 19 (PCM Frame Sync) - U4 WS
R6 P2 - U4 CLOCK
J1 GPIO 10 (SPI0 MOSI) - J2 1
J1 GPIO 8 (SPI Chip Select 0) - J2 4
J1 GPIO 20 (PCM Data-In) - U4 SD
J1 GPIO 9 (SPI0 MISO) - J2 2
J1 GPIO2 (I2C1 SDA) - U2 MISO/SDA
J1 GPIO 11 (SPI0 SCLK) - J2 8
BAT1 + - D1 Anode
R6 P2 - U4 CLOCK
J1 GPIO 11 (SPI0 SCLK) - J2 8
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 20 (PCM Data-In) - U4 SD
J1 GPIO 17 - J2 6
J1 GPIO 11 (SPI0 SCLK) - J2 3
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 11 (SPI0 SCLK) - J2 8
J1 GPIO 17 - J2 6
R7 P2 - U4 CLOCK
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 9 (SPI0 MISO) - J2 2
BAT1 + - D1 Anode
J1 GPIO 17 - J2 6
D1 Cathode - L1 P1
R6 P2 - U4 CLOCK
J1 GPIO 8 (SPI Chip Select 0) - J2 4
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO3 (I2C1 SCL) - U2 SCLK/SCL
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO3 (I2C1 SCL) - U2 SCLK/SCL
J1 GPIO 17 - J2 6
U1 VOUT - J1 5V PWR
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 3v3 - C4 P1
J1 GPIO 19 (PCM Frame Sync) - U4 WS
U1 VOUT - J1 5V PWR
D1 Cathode - L1 P1
J1 GPIO 11 (SPI0 SCLK) - J2 3
J1 GPIO2 (I2C1 SDA) - U2 MISO/SDA
J1 GPIO 20 (PCM Data-In) - U4 SD
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 8 (SPI Chip Select 0) - J2 4
R6 P2 - U4 CLOCK
J1 GPIO 10 (SPI0 MOSI) - J2 1
J1 3v3 - C4 P1
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
U1 VOUT - J1 5V PWR
J1 GPIO 17 - J2 6
J1 3v3 - C4 P1
J1 GPIO 17 - J2 6
J1 GPIO 11 (SPI0 SCLK) - J2 3
C3 P2 - L1 P2
J1 GPIO 11 (SPI0 SCLK) - J2 8
J1 GPIO 18 (PCM Clock) - U4 SCK
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 18 (PCM Clock) - U4 SCK
J1 3v3 - C4 P1
C2 P1 - U1 VI
R6 P2 - U4 CLOCK
J1 GPIO 17 - J2 6
J1 GPIO 20 (PCM Data-In) - U4 SD
J1 GPIO 18 (PCM Clock) - U4 SCK
D1 Cathode - L1 P1
J1 GPIO2 (I2C1 SDA) - U2 MISO/SDA
J1 GPIO 11 (SPI0 SCLK) - J2 3
J1 GPIO 10 (SPI0 MOSI) - J2 1
J1 GPIO 8 (SPI Chip Select 0) - J2 4
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
R7 P2 - U4 CLOCK
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 17 - J2 6
J1 GPIO 9 (SPI0 MISO) - J2 2
J1 GPIO 20 (PCM Data-In) - U4 SD
U1 VOUT - J1 5V PWR
J1 GPIO 17 - J2 6
J1 GPIO 20 (PCM Data-In) - U4 SD
J1 GPIO 17 - J2 6
C3 P2 - L1 P2
J1 3v3 - C4 P1
C16
Capacitance
Capacitance
C6
Capacitance
100nF
R3
Resistance
500 Ω
U5
C20
Capacitance
Capacitance
U2
Not Recommended for New Designs
R2
Resistance
500 Ω
C18
Capacitance
Capacitance
C7
Capacitance
100nF
C20
Capacitance
Capacitance
R9
Resistance
500 Ω
C2
Capacitance
Capacitance
R10
Resistance
500 Ω
MK1
C15
Capacitance
Capacitance
C13
Capacitance
Capacitance
U4
C11
Capacitance
Capacitance
R1
Resistance
500 Ω
R9
Resistance
500 Ω
R8
Resistance
500 Ω
R6
Resistance
22 Ω
C18
Capacitance
Capacitance
R5
Resistance
4.7kΩ
C19
Capacitance
Capacitance
R4
Resistance
4.7kΩ
R10
Resistance
500 Ω
C19
Capacitance
Capacitance
C17
Capacitance
Capacitance
C3
Capacitance
Capacitance
C18
Capacitance
Capacitance
R7
Resistance
22 Ω
C17
Capacitance
Capacitance
C8
Capacitance
100nF
R11
Resistance
500 Ω
C14
Capacitance
Capacitance
C21
Capacitance
Capacitance
C1
Capacitance
Capacitance
C21
Capacitance
Capacitance
R11
Resistance
500 Ω
C9
Capacitance
100nF
C4
Capacitance
Capacitance
R11
Resistance
500 Ω
C17
Capacitance
Capacitance
C12
Capacitance
Capacitance
C10
Capacitance
Capacitance
MK2
C5
Capacitance
100nF
C19
Capacitance
Capacitance
SW2
J1
TP_DC
TP_MOSI
GND
TP_CS
U3
J2
U6
TP_RST
TP_I2S_WS
TP_MISO
TP_BUSY
SW1
TP_I2S_CLK
TP_SDA
TP_SCK
U6
TP_I2S_SD
J2
TP_SCL
D1
Hole4
Hole3
BAT1
Hole2
Hole1
L1
Inductance
Inductance
REED1
U1

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    Particular Blue KITT

    Particular Blue KITT thumbnail
    Integration of 2.9" Raw E-Paper Display with Raspberry Pi using FPC and Dedicated PMIC Driver

    Properties

    Maintain 40–60 mm spacing between the two microphones for optimal beamforming.

    graph LR Pi[Pi Zero 2 W 40-pin header] MIC_L[Left PDM MEMS Microphone] MIC_R[Right PDM MEMS Microphone] EInk[2.9" E-Ink Display] NFC[NFC Tag IC] EEPROM[HAT ID EEPROM] Batt[AA Battery Pack] Boost[5V Boost Converter] SW_R[Reed Switch] SW_T1[Tactile Switch 1] SW_T2[Tactile Switch 2] Ant[13.56 MHz PCB Loop Antenna] Pi -- MOSI --> EInk Pi -- MISO --> EInk Pi -- SCK --> EInk Pi -- CS --> EInk Pi -- DC --> EInk Pi -- RST --> EInk Pi -- BUSY --> EInk Pi -- PDM_CLK --> MIC_L Pi -- PDM_CLK --> MIC_R Pi -- PDM_DAT --> MIC_L Pi -- PDM_DAT --> MIC_R Pi -- SDA --> NFC Pi -- SCL --> NFC Pi -- SDA --> EEPROM Pi -- SCL --> EEPROM Batt --> Boost --> Pi Pi -- GND --> GND Pi -- GPIO_R --> SW_R Pi -- GPIO_T1 --> SW_T1 Pi -- GPIO_T2 --> SW_T2 NFC -. Antenna .-> Ant

    [{"type":"erc_missing_power_pin_connection","data":{"designator":"U2","pin":7,"description":"Unconnected power pin (U2, pin 7: VDD_A)"}},{"type":"erc_missing_power_pin_connection","data":{"designator":"U2","pin":8,"description":"Unconnected power pin (U2, pin 8: VDD)"}},{"type":"erc_missing_power_pin_connection","data":{"designator":"U2","pin":9,"description":"Unconnected power pin (U2, pin 9: VDD_RF)"}},{"type":"erc_missing_power_pin_connection","data":{"designator":"U2","pin":10,"description":"Unconnected power pin (U2, pin 10: VDD_TX)"}},{"type":"erc_missing_power_pin_connection","data":{"designator":"U2","pin":11,"description":"Unconnected power pin (U2, pin 11: VDD_AM)"}},{"type":"erc_missing_power_pin_connection","data":{"designator":"U2","pin":14,"description":"Unconnected power pin (U2, pin 14: VDD_DR)"}}]

    Pin 1 (Gx) nearest PCB edge, orientation per panel datasheet

    Maintain 5 mm clearance around VGH, VGL, and VCOM nets

    mm

    40–60

    mm

    Pricing & Availability

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    TME

    $0.07

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    Controls