ESP8266 and LoRa PCB Design
Thought
Work done
- Saved and shared the required “System Architecture” Mermaid diagram (per the schematic workflow requirement)
- Added core parts:
- Started wiring (power, reset pullups, SPI nets to J2, etc.). The schematic wiring rule I am following requires fully pin-to-pin wiring before calling the schematic “complete”
Success criteria review
- ✅ ESP8266 power tree exists: USB -> 3.3 V reg -> 3V3 rail with 10 uF + 100 nF decoupling intent added
- ✅ EN/RST 10 kOhm pullups and a reset button exist (matches requirement and ESP8266 best-practice)
- ❌ USB-UART + auto-boot is not complete yet because the USB-UART bridge pins are not currently available to wire reliably (and the current ERC shows “Missing Power” errors)
- ❌ SX1276 breakout interface is not complete yet: J2 only has 8 pins, so DIO1 is not routed; also the exact header pin order needs confirmation
- ❌ Provision for future VIN + power-select jumper is not added yet
- ❌ ERC/DRC is not clean yet (open issues remain)
Next steps
- Confirm these 2 items so I can finish wiring without guessing:
- LoRa breakout header pin order: is it the common layout (3V3, GND, SCK, MISO, MOSI, NSS, RST, DIO0, DIO1), or different?
- Auto-boot: do you want the classic NodeMCU-style DTR/RTS -> GPIO0/RST transistor auto-program circuit, or manual BOOT only?
- After you confirm, I will:
- Fix the USB-UART placement/pins so U3 can be fully wired,
- Replace the LoRa header with a correct-pin-count header (so DIO1 is included),
- Add VIN header + power-select jumper,
- Finish RF/U.FL integration wiring,
- Re-run ERC/DRC until clean (per the “do not conclude with fixable violations” rule)
