Smart Chair Hardware Design Discussion
Thought for 3 mins 2 sec
Ergonix Smart Chair V1 — Hardware Design Description
- Overview
- Product: Ergonix Smart Chair V1 – smart seat module for occupancy, posture, and pressure distribution.
- Board: 2-layer target, 80 mm × 60 mm, USB‑C powered (5 V only), 3.3 V logic.
- Architecture: ESP32‑C3 module + I2C IMU + 4× FSR analog inputs + USB‑C power and ESD + JST‑PH harness connectors + LEDs, reset, and programming pads.
- Project stage: Pre‑prototype to Pilot (50–100 units); sourcing through LCSC for JLCPCB assembly.
- MVP functions
- Occupancy detection: FSR-based presence and basic thresholding.
- Sitting duration tracking: Periodic BLE updates to the app.
- Basic pressure mapping: 4 zones (front-left, front-right, back-left, back-right).
- Posture/tilt detection: IMU tilt channels (pitch/roll/yaw as needed).
- BLE connectivity: BLE link to the mobile app at 1 Hz for sensor data.
- Major hardware blocks
- MCU module: U1 ESP32‑C3‑WROOM‑02‑N4 (primary), fallback U2 ESP32‑C3‑WROOM‑02U‑N4 for external antenna option.
- IMU: U3 MPU‑6050 over I2C.
- Power input and protection:
- Sensor interfaces:
- User interface and debug:
- LEDs: D2, D3 with series resistors R17, R18.
- Reset: SW1 to U1:EN.
- Programming test pads: TP_PROG_TX, TP_PROG_RX, TP_BOOT, TP_EN.
- Grounds and return: GND single reference plane with short ESD return paths near the USB‑C connector.
- Power and USB‑C (power‑only)
- USB‑C sink behavior: Separate CC lines with Rd resistors:
- ESD/Surge: D1 on D+/D−; D4 on VBUS.
- Regulation: U4 generates 3.3 V; decouple with C1–C4 close to IN/OUT and add local 100 nF near U1 and U3.
- Native USB note: For V1, USB data is not connected to ESP32‑C3; programming uses UART test pads.
- I2C bus and peripherals
- Signals:
- Pull‑ups: 4.7 kΩ typical, placed near U1. Keep total bus capacitance within spec; the 30–50 cm harness is accounted for.
- FSR analog front‑end (4 channels)
- Harness: J2 carries 4 FSR sense lines plus power and ground.
- Per‑channel network (example, same pattern for all four):
- Notes:
- Series/input protection and RC filtering mitigate noise from long harness runs.
- ADC sampling at 1 Hz target; firmware to average a few samples for noise reduction.
- Calibration: per‑user software calibration; optional BOM‑tunable resistor footprints for range adjustments.
- User interface, reset, and programming
- LEDs:
- Reset:
- Programming/test:
- UART: TP_PROG_TX (TXD), TP_PROG_RX (RXD).
- Boot mode: TP_BOOT (IO0), TP_EN (EN).
- Pin map summary (current)
- ESP32‑C3 core pins (project nets):
- I2C: IO4 = SCL, IO5 = SDA.
- Programming: IO21 = PROG_TX (UART0 TX), IO20 = PROG_RX (UART0 RX), IO0 = BOOT, EN = reset.
- LEDs: IO6, IO7 used for indicator control.
- FSR: Four ADC channels wired to nets FSR1–FSR4 via the front‑ends listed above.
- Boot/strapping caution: IO0 and EN are strap/reset; avoid heavy loads or fixed external states during reset.
- RF and antenna plan
- Primary: U1 integrated PCB antenna at a board edge with a datasheet‑compliant keep‑out (no copper/vias/components in front of the antenna).
- Metal frame proximity: Validate RSSI/packet loss with the board mounted; if detuning occurs, pivot to U2 (external antenna option) with a remote antenna position away from metal.
- Connectors, harnessing, and mechanical
- USB‑C: J1 for power‑only.
- FSR harness: J2 6‑pin JST‑PH; route entries away from RF edge; add silkscreen pin‑1 marking.
- I2C/power harness: J3 4‑pin JST‑PH; exposes SDA/SCL/VCC/GND for IMU or expansion.
- Mounting: Place holes to avoid antenna aperture and thick structural members; keep cable egress clear of antenna region.
- ESD, protection, and grounding
- USB:
- CC detection:
- Ground strategy:
- Single reference plane; short ESD return to J1; keep analog returns (FSR filters) close to the plane and away from high‑dv/dt paths.
- BOM and sourcing snapshot
- All mains are LCSC‑backed; designed for JLCPCB assembly at qty‑100. Key line items by designator:
- Availability: Selected parts are common and stocked; alternates can be added if any supply constraints arise at order time.
- Firmware data and update cadence
- BLE data at 1 Hz: 4 FSR channels + basic IMU tilt; occupancy and duration counters as needed.
- Programming path: UART via TP_PROG_TX/TP_PROG_RX with TP_BOOT and TP_EN. Native USB not used in V1.
- Test and calibration plan (bring‑up)
- Power/USB: Verify no shorts; measure 5 V at J1 and 3.3 V at U4:OUT.
- Programming: Confirm boot into UART download with IO0 low at reset; flash a simple LED blink on D2/D3.
- I2C/IMU: Scan bus; read WHO_AM_I from U3.
- FSRs: Confirm analog ranges with known loads; perform software baseline calibration.
- RF soak: 8+ hour BLE link stability in chair frame environment; log RSSI/packet loss.
- Layout and DFM notes
- Antenna: Keep‑out per module datasheet; place U1 at a board edge with no copper/vias/components in front of the antenna.
- Analog vs digital: Keep FSR entries and RC filters away from USB and switching currents; short, direct ground returns to the plane.
- ESD: Place D1 and D4 close to J1 with minimal inductance in the return path.
- Open items and next steps
- Finalize routing and silkscreen keep‑out markings for the antenna aperture.
- Confirm I2C and FSR pin assignments at firmware integration time; avoid sharing IO6 between LED and FSR in the next spin if possible.
- Export manufacturing package: Gerbers, Pick‑and‑Place, and BOM CSV with LCSC numbers; attach assembly notes for the harness orientation and antenna placement.
- Revision control
- Current intent: V1 power‑only USB‑C, 4× FSR channels, integrated antenna primary, external antenna fallback via U2. Any changes to pin mapping or parts will be recorded in the project properties and reflected in the BOM.
This description reflects the current design state and is intended for internal alignment, firmware planning, purchasing (LCSC/JLCPCB), and mechanical integration.
shorter executive summary
firmware interface details
manufacturing notes expansion
test procedure checklist
mechanical constraints
Flux stopped
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