#Goal

- Prepare explicit PCB placement rules and grouping for key components on a 4-layer ESP32 audio recorder board. The goal is to specify placement zones and rules for USB-C and its VBUS protection chain, ESP32-WROOM-32 antenna with RF keep-out, clustered power path components (charger, buck converter, load switch), CH340E near USB-C, INMP441 away from noisy power areas, an accessible microSD socket, and a test-point cluster. No changes to the board outline are allowed.

#Implementation plan

1. Define board edge zones for critical components:

1. Place the USB-C connector (J2) and VBUS protection chain (PTC MF-PSMF050X-2 [F1], WE-TVS-82400102 [U8], 5V eFuse [U9]) near a defined board edge.

2. Set a placement rule to keep the ESP32-WROOM-32D (U1) antenna at a board edge and enforce an RF keep-out zone around its antenna region.

2. Group power path components:

1. Cluster the charger (BQ24074RGTT [U4]), buck converter (TPS560430X3FDBVR [U5]), and load switch (LTC2954CTS8-2#TRMPBF [U6]) in a single contiguous area to optimize VBUS-to-power path routing.

3. Set inter-component proximity rules:

1. Position the CH340E (U3) close to the USB-C connector (J2) to ease USB data routing.

2. Arrange the INMP441 (U7) away from the clustered power-path components to minimize noise interference.

3. Ensure the microSD socket (J1) is placed near an accessible board edge for easy access.

4. Define a test-point cluster area:

1. Create a region for test points (TP_VBUS, TP_SYS, TP_3V3, TP_I2S_WS, TP_SD_SCK, TP_EN, TP_GND) to facilitate debugging and validation.

5. Create PCB selector rules and assign tags for Auto-Layout:

1. Add tag properties such as [USB_Edge], [RF_Keepout], [PowerPath], and [AccessibleEdge] to the respective components to guide their placement.

2. Define explicit XY target rules and alignment constraints (e.g., row or column arrangement for protection chain and power path components) to minimize routing distances.

6. Document and verify rules:

1. Record placement zones and selector rules in the project metadata.

2. Review all placement rules to ensure compliance with the original board outline and design constraints.

#Success criteria

- USB-C (J2) and VBUS protection chain (F1, U8, U9) are verified to be placed near a board edge.

- ESP32-WROOM-32D (U1) antenna is correctly positioned at a board edge with an enforced RF keep-out zone.

- Charger (U4), buck converter (U5), and load switch (U6) are clustered to form a compact power path section.

- CH340E (U3) is adjacent to the USB-C connector (J2).

- INMP441 (U7) is placed away from the power path area.

- The microSD socket (J1) is accessible at a board edge.

- A dedicated test-point cluster is defined and accessible for debugging purposes.

- All placement rules and tags are documented in the project for Auto-Layout to enforce during component placement.

# Goal

- Refactor the schematic for the Careful Silver Tricorder project by replacing net portals with explicit wires and clear net labels, resolving ERC red concerns, and ensuring that all components have assigned footprints so they appear on the PCB. Then, prepare the PCB layout with a 4-layer stackup, defined layout rules (including RF keep-out restrictions), and use Auto-Layout with appropriate component grouping and routing.

# Implementation plan

1. Schematic Refactoring

1. Replace most net portals with explicit wires and add clear net labels to all connections.

2. Verify and add any missing reference nets (e.g., for VBUS, SYS, 3V3, I2S_WS, SD_SCK, EN, and GND) and group related signal labels.

3. Run ERC and address red alert warnings by validating connections and ensuring all net labels match component pins.

2. Footprint and ERC/DRC Synchronization

1. Confirm that all schematic components (U1 ESP32-WROOM-32D, U7 INMP441, J1 microSD socket, U3 CH340E, etc.) have valid assigned footprints.

2. Synchronize the schematic to the PCB layout so that all components are visible.

3. PCB Layout Preparation

1. Set up a 4-layer PCB stackup, assigning proper roles to each layer (Top, Inner1, Inner2, Bottom).

2. Define PCB rules including trace width, spacing, specific rules for power and clock nets, and RF keep-out areas (especially around U1 antenna areas).

3. Apply guidelines for grouping: cluster USB-C with VBUS protection, place CH340E near USB-C, cluster U4/U5/U6 for power management, and properly position INMP441 and microSD for signal integrity and accessibility.

4. Auto-Layout & Review

1. Run the Auto-Layout tool to place and route components according to the defined rules and grouping plan.

2. Review the layout for clearance, routing conflicts, and manufacturability.

5. Addressing the Empty PCB View

1. Verify that all components in the schematic have valid footprints linked to the PCB layout.

2. Ensure schematic-to-PCB synchronization is complete; fix any missing component or footprint associations that result in an empty PCB view.

# Success criteria

- All red ERC concerns are resolved and explicit wiring is visible in the schematic.

- Every component has a valid footprint and appears in the PCB layout.

- The PCB stackup is properly configured as a 4-layer board with designated RF keep-out areas.

- Auto-Layout completes with all parts placed and routed without errors, ensuring manufacturability and reliable operation.