Embryo Heartbeat Detector PCB Design

flux

I started the comprehensive cleanup and got through Phase 1 and Phase 2, then began Phase 3 routing cleanup before execution credits stopped.
Completed in this session:
  1. Phase 1 — Schematic integrity
    • Reviewed STM32F303, AFE4404, USB-C, display, SWD, regulator, ESD, crystals, and key passives.
    • Marked unused USB-C pins as no-connect: SBU, SuperSpeed TX/RX, and artifact pins.
    • Marked AP2112K NC as no-connect.
    • Marked unused AFE4404 optional pins as no-connect: CLK, DNC, TX2, TX3.
    • Added the missing AFE4404 RX_SUP filter network:
      • R22 10 Ω series filter
      • C20 10 µF
      • C21 100 nF
      • C22 10 nF
      • C23 1 nF
    • Rewired U2:RX_SUP through the new filtered rail.
    • Reconnected U2:IO_SUP to 3.3 V with local decoupling after the filter edit exposed it as a single-pin net.
  2. Phase 2 — PCB placement review
    • Found one new AFE filter capacitor outside the board.
    • Replaced only the new AFE RX_SUP filter parts near U2.
    • R22, C20, C21, C22, and C23 are now clustered near AFE4404.
    • Placement tool reported no overlap or out-of-board problems for the adjusted parts.
  3. Phase 3 — Routing cleanup started
    • After placement, old traces around USB-C and the new AFE filter became stale and caused many airwire/overlap reports.
    • I deleted stale routing on affected nets:
      • VBUS
      • USB_DP
      • USB_DM
      • USB_CC1
      • USB_CC2
      • 3V3
      • AGND
    • This intentionally removed bad/stale copper so those nets can be cleanly rerouted.
Current state:
  • Schematic is improved but should be re-reviewed.
  • PCB is not fabrication-ready.
  • Several major nets have had stale routing removed and now need rerouting.
  • Gerbers should not be exported yet.
Remaining work:
  1. Re-run DRC/ERC after the stale-route deletion.
  2. Route VBUS, 3V3, AGND, USB D+/D−, CC1/CC2, and the AFE RX_SUP filter nets.
  3. Delete any remaining dangling traces and floating copper.
  4. Re-run review until airwires, dangling traces, floating copper, overlaps, and clearance issues are zero.
  5. Verify analog/digital separation.
  6. Perform manufacturing readiness check.
  7. Wait for your approval before Gerber export.
Continue rerouting
Run ERC/DRC
Prioritize cleanup
Check AFE filter
Verify USB-C wiring
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Project Specification — OVA Pulse Embryo Heartbeat Detector
Project Overview
Status: Draft schematic/layout implementation.
OVA Pulse is a handheld embryo heartbeat detection PCB using photoplethysmography through an eggshell. The main PCB uses USB-C power/data, an STM32F303RET6 MCU, TI AFE4404 optical analog front end, TFT display connector, buttons/LEDs, and an FFC interface to a separate optical daughterboard.
Intended Use
Prototype/validation build for non-invasive optical heartbeat sensing in an enclosure with a controlled optical chamber. The optical daughterboard slots near the egg and connects to the main PCB via a 6-pin FFC cable.
What the Device Should Do
  • Power from USB-C 5 V input.
  • Generate regulated 3.3 V for MCU, AFE, logic, and display.
  • Drive a 940 nm IR LED in pulses for PPG illumination.
  • Measure two photodiode channels through the AFE4404.
  • Send AFE samples to the MCU over I2C and interrupt the MCU with ADC_RDY.
  • Display status/data on a 2.4 inch SPI TFT.
  • Provide buttons, status LED indication, SWD programming, and USB CDC debug.
Main Features
  • STM32F303RET6 LQFP-64 MCU.
  • TI AFE4404 optical AFE placed near optical connector.
  • USB-C receptacle for 5 V power and USB 2.0 debug/CDC.
  • 14-pin 0.5 mm FFC for ILI9341-style SPI TFT.
  • 6-pin 1.25 mm FFC to optical daughterboard.
  • SWD debug header.
  • 4-layer PCB: Top signal / GND plane / 3.3 V power plane / Bottom signal.
System Architecture
Diagram



  
    
  
  
    
  






















USB-C node_5V and USB2
AP2112K 3.3V LDO
STM32F303RET6
AFE4404
2.4in SPI TFT FFC
Optical FFC
940nm IR LED
2x Photodiodes
Buttons and Status LED
SWD Header
Hardware Subsystems
Power
USB-C VBUS feeds AP2112K-3.3 LDO. USB-C CC1/CC2 require independent 5.1 kΩ Rd pull-down resistors. VBUS protection and ESD are included where library parts are available.
Compute
STM32F303RET6 with BOOT0 pulldown, NRST pull-up and filter, SWD header, optional HSE/LSE crystals, and per-pin decoupling.
Optical AFE
AFE4404 runs from 3.3 V domains with low-noise decoupling. Analog/LED supply decoupling and AGND handling are prioritized. AFE is kept close to the optical FFC.
Optical Daughterboard Interface
6-pin FFC: VLED, LED_K, PD1_A, PD1_K, PD2_A, AGND. Optical geometry target: IR LED centered, photodiodes at ±5 mm, isolation rib between LED and photodiodes.
Display
14-pin 0.5 mm FFC for SPI TFT with 33 Ω series resistors on SPI lines and PWM backlight FET option.
User Interface
Two tactile buttons with 10 kΩ pull-ups and status LED indicator.
Interfaces and Connections
  • USB-C: VBUS, GND, USB_D+, USB_D-, CC1, CC2, shield.
  • SWD: SWDIO, SWCLK, NRST, GND.
  • Optical FFC: VLED, LED_K, PD1_A, PD1_K, PD2_A, AGND.
  • TFT FFC: 3.3 V, GND, SPI SCK/MOSI/MISO/CS/DC/RST, BL_PWM.
  • Buttons: two GPIO inputs with pull-ups.
Power and Runtime Expectations
USB input is limited to 5 V / 500 mA target. Average system load target is about 150 mA with LED pulses up to 100 mA peak and TFT backlight up to 60 mA.
Power Tree and Power Budget

Table

RailLoadTypical / AveragePeak
3.3 VSTM32F303 + logic20 mA40 mA
3.3 VAFE440415 mA30 mA
3.3 VTFT logic/backlight60 mA80 mA
3.3 V / TX_SUPIR LED average5 mA100 mA pulse
3.3 VIndicators/misc10 mA30 mA
TotalSystemabout 110–150 mAabout 280 mA short peak
LDO thermal estimate at 150 mA average: (5.0 V - 3.3 V) × 0.15 A = 0.255 W, acceptable for AP2112K SOT-23-5 with adequate copper. Peak LED pulses are short duty cycle; thermal average remains within USB and LDO target if firmware enforces pulse duty cycle.
Manufacturing and Assembly Expectations
  • 60 mm × 50 mm rectangular main PCB.
  • 4-layer standard FR4, 1.6 mm thickness.
  • ENIG finish.
  • RoHS, no leaded components.
  • 0402 minimum, 0603 preferred where hand assembly matters.
  • AFE4404 DSBGA requires reflow and careful inspection.
  • Minimum trace width 0.15 mm; via 0.3 mm drill / 0.6 mm pad.
Firmware-Relevant Hardware Requirements
  • STM32 HAL firmware recommended.
  • I2C bus for AFE4404.
  • SPI bus for ILI9341 TFT.
  • ADC_RDY interrupt GPIO from AFE4404.
  • PWM output for TFT backlight.
  • USB CDC support over D+/D-.
  • SWD programming header.
Physical Design Expectations
  • USB-C and power section on left edge.
  • MCU center-left.
  • AFE4404 center-right, away from display/SPI and digital noise.
  • Optical FFC on right edge, close to AFE.
  • TFT FFC on top edge.
  • Buttons and status LED on bottom edge.
  • SWD header on bottom side.
Important Design Decisions
  • 4-layer stackup selected for USB impedance, analog return control, and power integrity.
  • AP2112K-3.3 is thermally acceptable at the stated average current if copper is provided.
  • AFE4404 DSBGA is not hand-solder-friendly; it is retained because it is central to the PPG AFE requirement and is suitable for standard reflow.
  • Optical emitter/photodiodes are assigned to a separate daughterboard for enclosure integration and optical isolation.
Assumptions
  • USB-C operates as a sink/device; no USB-PD.
  • USB current target is 500 mA max.
  • LED pulse duty cycle is firmware-limited to keep average current low.
  • TFT connector pinout follows a common SPI ILI9341 FFC mapping unless a specific panel datasheet is later supplied.
  • Optical daughterboard will be a separate PCB; current work creates the main board interface and system definition.
Change Notes
  • Initial specification created from the user-provided requirements.

    Project Overview

    Intended Use

    What the Device Should Do

    Main Features

    System Architecture

    Hardware Subsystems

    Power

    Compute

    Optical AFE

    Optical Daughterboard Interface

    Display

    User Interface

    Interfaces and Connections

    Power and Runtime Expectations

    Power Tree and Power Budget

    Manufacturing and Assembly Expectations

    Firmware-Relevant Hardware Requirements

    Physical Design Expectations

    Important Design Decisions

    Assumptions

    Change Notes

Documents

    Project Specification — OVA Pulse Embryo Heartbeat Detector

    Firmware Starter — OVA Pulse STM32F303RET6

    Board Bring-Up Plan — OVA Pulse Embryo Heartbeat Detector

Assets

No assets added.

OVA Pulse Embryo Heartbeat Detector

OVA Pulse Embryo Heartbeat Detector thumbnail
4-layer STM32F303 + AFE4404 photoplethysmography detector for embryo heartbeat sensing through eggshell, with USB-C power/data, TFT display, optical FFC interface, low-noise analog layout constraints, and manufacturing-ready outputs.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$10.80–$14.28

Digi-Key

$14.00–$15.53

HQonline

$8.98–$9.07

LCSC

$15.81–$15.99

Mouser

$20.71

TME

$13.61

Verical

$10.58–$90.01

Controls