Quad BLDC Drone ESC Design

Added the ESC-side power input interface:
  • J21: Würth REDCUBE M5 lug for PM_6S_PROTECTED
  • J22: Würth REDCUBE M5 lug for GND
  • J23: 5-pin low-current header for 3V3_A and GND, with one spare pin marked no-connect
Focused ERC/connectivity check found no new issues for J21–J23.
Define the SPI mezzanine pinout between the ESC and flight controller with spare pins.
I’ll define a practical SPI mezzanine pinout for the stacked ESC ↔ flight-controller interface with grounds, reset/fault lines, temperature telemetry support, and spare pins, then record it in the project notes/spec.
Defined the ESC ↔ flight-controller mezzanine pinout in Project Specification.
Summary:
  • 60-pin ERM8/ERF8-style pinout.
  • Shared SPI bus with separate CS/INT/FAULT/RESET/READY for STM32 U1 and U2.
  • Includes heartbeat, sync, arm/safe lines, 18 ground pins, and 18 spare/reserved pins.
  • High-current 6S power stays off the mezzanine connector.
Add mezzanine connector
Assign MCU pins
Run full ERC
Review connector sourcing
Prepare PCB placement

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Project Specification — Quad BLDC Drone ESC
Project Overview
Status: Draft schematic architecture.
Design a single-board drone ESC powered from a nominal 22 V battery, controlling four independent Hall-sensored BLDC motors. The selected low-cost architecture uses 4 × DRV8308 sensored BLDC controller/predrivers and 2 × STM32G474CBT6 microcontrollers for supervision, configuration, telemetry, command handling, and inter-MCU coordination.
Intended Use
  • Drone propulsion ESC board for four independent BLDC motors.
  • Prototype/architecture stage; main schematic components are being added first, followed by supporting passives, MOSFET power stages, protection, sensing, and firmware documentation.
  • Motor current sizing basis for initial MOSFET and copper sizing: 20 A continuous, 36 A max, and 52 A peak spike per motor. Motor KV, pole count, board size, cooling, firmware update interface, and some mechanical constraints remain open.
What the Device Should Do
  • Control four Hall-sensored BLDC motors from one PCB.
  • Use one DRV8308 per motor channel.
  • Use each DRV8308 for Hall-based commutation and motor-speed control.
  • Use STM32G474 MCUs to configure DRV8308 registers over SPI, command speed/direction, monitor faults, coordinate channels, and communicate with the flight controller.
  • Provide external motor phase outputs and Hall sensor connections for each motor.
Main Features
  • Input: 22 V nominal battery bus.
  • Compute: 2 × STM32G474CBT6, 3.3 V logic.
  • Motor control: 4 × DRV8308, each driving 6 external N-channel MOSFETs for one 3-phase BLDC motor.
  • Feedback: 3 Hall sensor channels per motor connected to the corresponding DRV8308.
  • Telemetry: temperature-only telemetry exposed through the flight-controller interface.
  • No onboard datalink transmitter or receiver on the drone.
  • Debug/programming: SWD connector per MCU recommended.
  • ESC ↔ flight-controller interface: SPI, selected for fast low-cost communication in a stacked-board architecture.
  • Inter-MCU link: SPI preferred unless pin routing or firmware partitioning favors FDCAN internally.
System Architecture

Diagram


"Inter-MCU link" "22 V Battery" "Input Protection + Bulk Capacitance" "3.3 V / auxiliary rails" "3-Phase Inverter M1" "3-Phase Inverter M2" "3-Phase Inverter M3" "3-Phase Inverter M4" "STM32G474 #1" "STM32G474 #2" "DRV8308 M1" "DRV8308 M2" "DRV8308 M3" "DRV8308 M4" "BLDC Motor 1 + Hall" "BLDC Motor 2 + Hall" "BLDC Motor 3 + Hall" "BLDC Motor 4 + Hall"
Hardware Subsystems
Power Input and Protection
  • 22 V nominal battery input; exact chemistry and voltage range TBD.
  • Needs reverse-polarity protection, TVS surge protection, fuse/current protection, low-ESR bulk capacitance, and per-inverter ceramic decoupling.
  • Must be sized from motor stall/peak current, not nominal voltage alone.
Microcontrollers
  • STM32G474CBT6 is suitable for control/supervisory firmware: Cortex-M4F, high-resolution timers, advanced motor timers, ADCs, op-amps, comparators, CORDIC/FMATH accelerators, SPI/UART/FDCAN.
  • In this DRV8308 architecture, the MCU does not directly generate six PWM gate signals per motor; it commands/configures DRV8308 channels.
  • Two motors per MCU is reasonable for supervisory control, SPI programming, command generation, fault monitoring, and telemetry.
Motor
  • Selected motor: Skystars Koko 2207.5 / 2275 1950KV, intended for 6S LiPo and 5-inch propellers.
  • Motor source: https://www.rotorama.com/product/skystars-koko-2207-5-1950kv
  • Key motor specs: 1950KV, 2207.5 stator, 12N14P, 5 mm shaft, 16×16 mm M3 mounting, 32 g, 20 AWG 150 mm leads.
  • Current basis: published secondary listing indicates 36 A max for 180 s and 1000 W max continuous power for 180 s; design continues to assume 20 A continuous, 36 A max, and 52 A transient spike per motor.
  • Use 4 × DRV8308, one per BLDC motor.
  • Each DRV8308 drives 6 external N-channel MOSFETs.
  • Initial MOSFET selection for each inverter switch: Vishay SiR680ADP-T1-RE3, 80 V N-channel PowerPAK SO-8, RDS(on) 2.88 mΩ max at VGS = 10 V, Flux UID 7dd3f499-5e82-4684-9088-702c9a94720b.
  • Each motor channel needs: DRV8308, 6 MOSFETs, bootstrap/charge-pump support components, current-limit sense resistor path, motor phase connector, Hall connector, bulk/ceramic bus capacitance, and fault/speed/control signals to MCU.
  • DRV8308 supports Hall-based commutation and optional closed-loop speed control; this is not true MCU-run FOC.
Interfaces and Connections
  • Battery input connector: current rating TBD.
  • Four motor phase connectors: U/V/W per motor.
  • Four Hall sensor connectors: Hall U/V/W plus Hall supply and ground per motor.
  • Flight-controller command/telemetry interface: SPI. It must carry motor commands into the ESC and temperature-only telemetry back to the flight controller.
  • SPI is selected because the boards are expected to be stacked or connected over a short board-to-board interconnect, making external transceivers unnecessary.
  • Board-to-board connector: Samtec TFC/SFC and TFM/SFM Tiger Eye 30-contact options were checked for the stacked ESC/flight-controller SPI interface, but the matching header configurations are marked Existing Customers Only by Samtec. Do not commit those footprints unless procurement confirms access.
  • Current implementable fallback in Flux: Samtec ERM8/ERF8 0.80 mm Edge Rate mezzanine family, 60 contacts, 10 mm stack height, SMT footprints available in Flux. This is more pins/cost than the original 30-contact target but gives ample spare pins and rugged board-to-board mechanics.
  • No datalink radio/transmitter/receiver is to be included on the drone electronics.
  • Inter-MCU communication: SPI preferred for low cost and speed; define master/slave ownership during firmware architecture.
  • Programming/debug: SWD + reset per STM32.
Power and Runtime Expectations
  • Battery system: 6S LiPo, 22.2 V nominal, approximately 25.2 V fully charged and approximately 18.0 V at conservative discharge cutoff.
  • User prefers the battery/power-management function on a separate board, but would like it incorporated onto the flight controller if space and thermal/current routing allow.
  • Logic rails: 3.3 V for STM32 and logic.
  • DRV8308 motor supply: 8.5–32 V operating range, compatible with nominal 22 V if battery maximum remains below 32 V.
  • Hall supply: DRV8308 includes 5 V regulator output for Hall sensors, limited current per datasheet; verify total Hall sensor current.
  • Motor bus: 22 V nominal, final min/max TBD.
Power Tree and Power Budget

Table


RailSourceLoadsCurrent Status
6S BATExternal 6S LiPo packPower-management board / flight-controller power inputPack connector, fuse, reverse-polarity protection, TVS, current/voltage monitor TBD
Protected VBAT outputsPower-management boardESC board, flight controller, E/O cameraEach downstream board needs its own surge/current protection path
VBAT / VMOTORProtected 6S outputFour inverter stages, 4 × DRV8308 VM20 A continuous per motor / 80 A board continuous; 36 A max per motor / 144 A board max; 52 A spike per motor / 208 A board simultaneous spike case
3.3 VBuck regulator from battery2 × STM32G474, logic, commsTBD after component selection
5 V HallDRV8308 VREG5 per channel or external 5 VHall sensorsHall current TBD
Required before power-path sizing:
  • Downstream boards to be powered, with voltage/current requirements for each board.
  • Per-motor current basis: 20 A continuous, 36 A max, 52 A peak spike. Spike duration and repetition rate still TBD.
  • Motor KV, pole count, maximum RPM, and Hall sensor voltage/current.
  • Cooling assumptions: airflow, copper area, enclosure constraints.
Power-Management / Flight-Controller Integration Direction
  • Add a 6S power-management board function that accepts the battery pack and distributes protected power to the ESC, flight controller, and E/O camera.
  • Provide surge protection for each powered board output, not just one shared input TVS.
  • Recommended protection per high-current output: appropriately rated fuse/eFuse or current limiter, TVS diode to power ground, reverse-current/reverse-polarity strategy as needed, local bulk capacitance, and connector sized from the target load current.
  • Telemetry requirement: temperature telemetry only. Do not add battery/current telemetry as a user-facing telemetry requirement unless later requested.
  • Recommended temperature sensing locations: ESC power stage/MOSFET area, DRV8308/driver area, regulator/power-management hot spot, flight-controller board hot spot, and E/O camera power output/regulator hot spot if present.
  • User-requested thermal sensing: add one temperature sensor near each MOSFET bridge, plus sensors at power-management hot spots including battery input/protection and main regulator/current-distribution area. Temperature data is reported through the SPI flight-controller interface.
  • Integration decision: keep the power-management function separate unless the flight-controller PCB has enough area for high-current copper, thermal relief, connector clearance, and noise isolation from IMU/radio/MCU circuitry. If incorporated onto the flight controller, separate the high-current battery path physically from sensors and low-noise analog sections.
Manufacturing and Assembly Expectations
  • High-current ESC layout requires at least 4-layer PCB with heavy copper and very wide pours. Initial recommendation: 2 oz copper minimum, 3–4 oz preferred for the ESC power board if 80 A continuous is realistic.
  • 80 A continuous board-current sizing cannot be handled as a normal trace. Use broad top/bottom VBAT and PGND pours, dense via stitching, short high-current loops, and possibly solder-thickened exposed copper or busbar-style reinforcement.
  • IPC-2221 external-copper estimate for 80 A continuous: with 4 oz copper, ~20.8 mm width for 20°C rise or ~16.3 mm for 30°C rise; with 3 oz copper, ~27.7 mm for 20°C rise or ~21.7 mm for 30°C rise.
  • Thermal design and current-limit sense layout are critical.
  • DRV8308 VQFN and high-current MOSFET layout are not beginner-friendly for hand assembly.
Firmware-Relevant Hardware Requirements
  • Per DRV8308: SPI configuration path or programmed NVM strategy, speed command, direction, enable, fault output, lock/status, optional FG/speed feedback.
  • Per motor: Hall U/V/W inputs to DRV8308.
  • Per MCU: SWD, boot/reset, debug UART, watchdog/failsafe behavior.
  • Firmware architecture must define master/slave behavior or partition two motors per MCU.
  • Flight-controller interface firmware must report temperature-only telemetry and must not depend on an onboard datalink radio.
  • SPI protocol must include command framing, temperature telemetry frames, fault/status bits, CRC or checksum, and timeout/failsafe behavior.
Physical Design Expectations
  • Board partition decision locked: use two separate PCBs — one ESC PCB and one power-management PCB.
  • Each PCB must independently fit within a maximum footprint of approximately 60 mm width × 200 mm length.
  • Treat 60 mm as the controlling dimension for high-current bus layout, connector placement, mounting holes, airflow, and heatsinking.
  • High-current power paths should run lengthwise where possible so 40–50 mm equivalent copper/busbar width can be preserved without consuming the whole board width.
  • Mounting holes, connector placement, airflow, and heatsinking details are still TBD within this footprint.
  • Keep motor phase loops compact and separate noisy power stages from MCU analog references.
  • Place each DRV8308 close to its MOSFET bridge and current-sense path.
  • Verified but not recommended for new design unless procurement confirms access: Samtec TFC-115-22-F-D-A + SFC-115-T2-F-D-A, 30 contacts, 1.27 mm pitch, SMT, 10.00 mm mated stack height per SFC/TFC catalog; Samtec product pages mark the parts Existing Customers Only.
  • Verified but not recommended for new design unless procurement confirms access: Samtec TFM-115-22-L-D-A + SFM-115-02-L-D-A, 30 contacts, 1.27 mm pitch, SMT, rugged Tiger Eye family; header availability is restricted/Existing Customers Only.
  • Selected implementable footprint direction: Samtec ERM8-030-05.0-S-DV-K-TR header + ERF8-030-05.0-S-DV-L-K-TR socket, 60 contacts, 0.80 mm pitch, SMT, 10.00 mm mated height with -05.0/-05.0 lead styles. Flux library parts found: ERM8 UID 3747610b-dcb6-4a0d-8325-7892b232f832 and ERF8 UID 4df3cff0-3881-4448-a4fa-8b5cf137c179.
  • Caveat: Samtec product pages for ERM8/ERF8 configurations also show Existing Customers Only notices, so procurement must confirm orderability before layout release. If procurement cannot source them, create/import an available Molex SlimStack 10 mm pair or another open-order Samtec alternate before PCB layout.
  • Rationale: ERM8/ERF8 has verified 10 mm stack-height documentation, rugged/high-speed board-to-board construction, available Flux footprints, and 60 contacts for generous spare pins. Avoid using the connector as the only mechanical support; add 10 mm standoffs near the connector.
  • Reserve enough pins for SPI SCLK/MOSI/MISO/CS, interrupt/data-ready, reset or enable, shared ground returns, 3.3 V reference/logic supply if needed, temperature-alert lines if used, and spare GPIOs. With the 60-contact ERM8/ERF8 fallback, target at least 20 spare/ground pins after assigning required SPI, control, power-reference, and ground pins.
  • Keep SPI traces short, length-matched only if clock speed requires it, and interleave/adjacent ground pins where possible to improve signal integrity across the stack.
ESC ↔ Flight-Controller SPI Mezzanine Pinout
Connector target: 60-contact, 2-row mezzanine footprint compatible with the selected Samtec ERM8/ERF8 30-position dual-row direction. Flight controller is the SPI master. ESC-side STM32 U1 and U2 are independent SPI targets sharing SCLK/MOSI/MISO but using separate chip-select, interrupt, reset, ready, and fault lines. This pinout is signal/control only; high-current 6S power remains on REDCUBE lugs and regulated ESC logic power comes from the power-management board.

Table


PinSignalDirectionPurpose
1GNDReturn / shield
2GNDReturn / shield
3FC_SPI_SCKFC → ESCShared SPI clock
4GNDReturn adjacent to SCK
5FC_SPI_MOSIFC → ESCShared SPI controller-to-ESC data
6GNDReturn adjacent to MOSI
7FC_SPI_MISOESC → FCShared SPI ESC-to-controller data
8GNDReturn adjacent to MISO
9ESC_U1_CS_NFC → ESCChip-select for STM32 U1 / motors 1–2
10ESC_U2_CS_NFC → ESCChip-select for STM32 U2 / motors 3–4
11ESC_U1_INT_NESC → FCU1 interrupt/data-ready
12ESC_U2_INT_NESC → FCU2 interrupt/data-ready
13ESC_U1_FAULT_NESC → FCU1 aggregated motor/driver fault
14ESC_U2_FAULT_NESC → FCU2 aggregated motor/driver fault
15ESC_U1_RESET_NFC → ESCReset U1 from flight controller
16ESC_U2_RESET_NFC → ESCReset U2 from flight controller
17ESC_U1_READYESC → FCU1 firmware ready/healthy
18ESC_U2_READYESC → FCU2 firmware ready/healthy
19FC_HEARTBEATFC → ESCFlight-controller heartbeat / failsafe monitor
20ESC_SYNCFC → ESCOptional command-frame sync / timebase strobe
213V3_IO_REFFC ↔ ESCLogic-level reference only; current-limited, not primary power
22GNDReturn for reference/control signals
23ESC_ARM_ENABLEFC → ESCHardware arming gate / safety enable
24ESC_SAFE_STATE_NFC → ESCOptional forced-safe / inhibit line
25FC_UART_TX_SPAREFC → ESCSpare debug UART TX or GPIO
26FC_UART_RX_SPAREESC → FCSpare debug UART RX or GPIO
27I2C_SCL_SPAREBidirectionalSpare low-speed expansion
28I2C_SDA_SPAREBidirectionalSpare low-speed expansion
29AUX_TX_SPAREFC → ESCSpare GPIO/UART/CAN-reserved signal
30AUX_RX_SPAREESC → FCSpare GPIO/UART/CAN-reserved signal
31GNDAdditional return / shield
32GNDAdditional return / shield
33SPARE_GPIO1TBDSpare
34SPARE_GPIO2TBDSpare
35SPARE_GPIO3TBDSpare
36SPARE_GPIO4TBDSpare
37GNDAdditional return / shield
38GNDAdditional return / shield
39SPARE_GPIO5TBDSpare
40SPARE_GPIO6TBDSpare
41SPARE_GPIO7TBDSpare
42SPARE_GPIO8TBDSpare
43GNDAdditional return / shield
44GNDAdditional return / shield
45SPARE_GPIO9TBDSpare
46SPARE_GPIO10TBDSpare
47SPARE_GPIO11TBDSpare
48SPARE_GPIO12TBDSpare
49GNDAdditional return / shield
50GNDAdditional return / shield
51RESERVED_1TBDReserved for future telemetry/control
52RESERVED_2TBDReserved for future telemetry/control
53RESERVED_3TBDReserved for future telemetry/control
54RESERVED_4TBDReserved for future telemetry/control
55GNDAdditional return / shield
56GNDAdditional return / shield
57MECH_ID0Passive/TBDOptional board ID / strap
58MECH_ID1Passive/TBDOptional board ID / strap
59GNDEnd return / shield
60GNDEnd return / shield
Pinout rules:
  • Do not carry motor/battery current through the mezzanine connector.
  • Treat 3V3_IO_REF as a logic-level reference or very-low-current sense rail only; ESC MCU power remains on the power-management 3V3_A rail.
  • Keep SPI pins adjacent to ground returns and route SCK/MOSI/MISO as short controlled-return traces across the stack.
  • Firmware must implement CRC/checksum, command timeout, hardware arm gating, and safe motor shutdown if SPI heartbeat is lost.
Important Design Decisions
  • Architecture locked by user: choose cheaper 4 × DRV8308 sensored BLDC approach instead of true FOC.
  • One DRV8308 controls exactly one BLDC motor.
  • Back-EMF sensing is not the primary control method in this architecture; Hall sensors drive commutation.
  • Battery system locked by user: 6S 22.2 V nominal pack.
  • New system requirement: design a power-management/distribution board with surge protection for every downstream board it powers; evaluate incorporating this function onto the flight controller if board space and noise/thermal constraints permit.
  • Downstream powered boards locked by user: ESC, flight controller, and E/O camera for autonomous flying.
  • Telemetry decision locked by user: temperature telemetry only, accessed through the flight-controller interface; no drone-mounted datalink transmitter or receiver.
  • Interface decision locked by user: SPI between stacked ESC and flight-controller boards for fastest communication at low manufacturing cost.
  • Connector decision locked by user: low-cost board-to-board mezzanine connector for the SPI stack.
  • Stack-height decision locked by user: 10 mm spacing between ESC and flight-controller PCBs.
  • Connector verification result: original Samtec low-cost Tiger Eye TFC/SFC 30-contact option meets 10 mm stack height but is restricted by Samtec as Existing Customers Only. Use ERM8/ERF8 Flux footprints as the current implementable option, subject to procurement confirmation.
  • Power-stage sizing note created: see Power Stage Sizing Notes for MOSFET selection, copper-width calculations, stackup assumptions, and temperature-sensor placement.
  • Board partition locked by user: separate ESC PCB and power-management PCB, each with its own 60 mm × 200 mm maximum footprint.
  • SPI mezzanine pinout defined for the 60-contact ERM8/ERF8-style connector: shared SPI bus, independent U1/U2 CS/INT/FAULT/RESET/READY lines, heartbeat/sync/arming lines, 18 ground pins, and 18 spare/reserved pins.
Assumptions
  • 22 V battery means nominal voltage; actual min/max not yet confirmed.
  • Four motors are independent propulsion channels.
  • User wants one PCB, not four separate ESC modules.
  • DRV8308 open-loop/closed-loop speed control is acceptable versus true torque FOC.
Open Questions Blocking Final Power-Stage Sizing
  1. What are the remaining motor specs: voltage, KV, pole count, 36 A max duration, 52 A spike duration/repetition rate, and Hall sensor current?
  2. What current and voltage rails are required by the flight controller and E/O camera?
  3. Confirm connector procurement access, then create the SPI stack pinout using the selected ERM8/ERF8 60-contact footprint or an approved open-order alternate.
  4. Within the 60 mm × 200 mm maximum footprint, what exact board split, mounting-hole pattern, and airflow/cooling assumptions should be used?
  5. Should DRV8308 configuration be done by SPI at every boot, external EEPROM, or OTP programming?
  6. What temperature sensor topology should be used: analog NTC thermistors to STM32 ADCs, digital I2C/SPI temperature sensors, or both?
Change Notes
  • User selected the cheaper DRV8308 approach.
  • Architecture updated to 4 × DRV8308, one per motor, with Hall-sensor feedback.
  • User specified a separate 6S 22.2 V battery/power-management board concept, with preference to integrate onto the flight controller if feasible.
  • User specified powered downstream boards: ESC, flight controller, and E/O camera.
  • User specified temperature-only telemetry through the flight controller interface and no onboard datalink transmitter/receiver.
  • User selected SPI for the ESC ↔ flight-controller interface because the boards may be stacked.
  • User requested a low-cost board-to-board mezzanine connector for the SPI stack.
  • User specified 10 mm stack height between ESC and flight-controller boards.
  • Samtec connector drawings were checked. TFC/SFC 30-contact option gives 10.00 mm stack height but is Existing Customers Only. ERM8/ERF8 60-contact 10 mm option has Flux footprints and is the current implementable fallback, but procurement access still needs confirmation.
  • User specified motor current basis for initial sizing: 20 A continuous per motor, 36 A max per motor, and 52 A peak current spike per motor. Four-motor board-level cases are 80 A continuous, 144 A max, and 208 A simultaneous spike.
  • Initial MOSFET selected for sizing: Vishay SiR680ADP-T1-RE3, 80 V PowerPAK SO-8.
  • User requested temperature sensors near each MOSFET bridge and power-management hot spots.
  • Initial copper/stackup recommendation added: 4-layer minimum, 2 oz minimum copper, 3–4 oz preferred for the ESC power board, with wide pours/busbar-style distribution for 80 A continuous.
  • User specified that all PCB boards must fit within an approximate maximum footprint of 60 mm width × 200 mm length.
  • User confirmed separate ESC and power-management PCBs, each independently limited to approximately 60 mm × 200 mm maximum footprint.
  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Power Input and Protection

  • Microcontrollers

  • Motor

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Power-Management / Flight-Controller Integration Direction

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • ESC ↔ Flight-Controller SPI Mezzanine Pinout

  • Important Design Decisions

  • Assumptions

  • Open Questions Blocking Final Power-Stage Sizing

  • Change Notes

Interceptor 3948 thumbnail
Quad BLDC Drone interceptor with dual STM32G474 controllers, sensored motor feedback, and 22 V battery input.

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