Finding Unipi Component
Thought for 1 sec
- Renamed +3.3 to +3.3V_1
- Renamed JP6 to +3.3V_2
- Renamed JP14 to +3.3V_3
- Renamed JP11 to +3.3V_4
- Renamed JP1 to +3.3V_5
- Renamed JP4 to +3.3V_6
- Renamed JP18 to +3.3V_7
- Renamed JP20 to +3.3V_8
- Renamed JP10 to +3.3V_9
- Renamed +5 to +5V_1
- Renamed JP5 to +5V_2
- Renamed JP13 to +5V_3
- Renamed JP12 to +5V_4
- Renamed JP2 to +5V_5
- Renamed JP15 to +5V_6
- Renamed JP19 to +5V_7
- Renamed JP21 to +5V_8
- Renamed JP9 to +5V_9
- Renamed JP3 to +12_5
- Renamed JP16 to +12_6
- Renamed JP17 to +12_7
- Renamed JP22 to +12_8
- Renamed JP8 to +12_9
- Renamed JP7 to +12_10
Thought for 6 sec
Work done
- Renamed all SolderJumper 2 Open components so their designators now use the requested source-rail prefixes:
+12_,+5V_, and+3.3V_. - Verified the schematic now has no old
JPjumper designators remaining, and the existing jumper properties/connections are still present after the designator-only rename. - Documented the convention in Design Notes.
- ✅ Jumpers use rail-based prefixes.
- ✅ Numbering is unique within each rail group.
- ✅ No old JP-numbered SolderJumper designators remain.
- ✅ Project notes document the naming convention.
- The schematic jumper naming cleanup is complete. If you want, I can next proceed with PCB layout cleanup or check the remaining duplicate/non-jumper designator issues.
Check duplicate designators
Run ERC/DRC review
Inspect layout labels
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Design Notes
Architecture
- Passive connector-hub PCB under a UniPi 1.1 board.
- No active circuitry; schematic limited to connectors, 0-ohm links, and direct net routing.
- Enclosure target: 30 x 40 x 10 mm.
- Internal connectors: straight 5.08 mm pitch, placed on top side.
- External connectors: straight 3.81 mm pitch, placed on bottom side.
- Power entry: ATX 24-pin connector providing 12V, 5V, 3.3V, and GND.
Mapping Assumptions In Force
- I2C is replicated to 6 external 4-pole connectors using the standard order GND, 3.3V, SDA, SCL.
- Serial is mapped to 1 external 4-pole connector using the order GND, logic supply reference, TX, RX.
- Remaining UniPi outputs use 2-pole field connectors.
- Remaining UniPi inputs use 4-pole field connectors.
- 0-ohm links are used as configurable forwarding jumpers for 12V, 5V, and 3.3V to the relevant external supply positions.
Open Dependency
- Exact UniPi 1.1 connector pin inventory and physical pinout are still needed for a true 1:1 implementation. Until that mapping is available in the project, the design can only establish the board framework, connector families, and layout envelope, not the final verified pin-to-pin breakout table.
- Uploaded technical documentation confirms that UniPi 1.1 exposes UART and I2C on RJ11 connectors, not JST connectors.
- UART RJ11 pinout in the uploaded manual: pin 2 = 5V, pin 3 = RX, pin 4 = TX, pin 5 = GND.
- I2C RJ11 pinout in the uploaded manual: pin 2 = 5V, pin 3 = SDA, pin 4 = SCL, pin 5 = GND.
- The uploaded manual confirms external I/O counts at a high level (8 relays, 12+2 digital inputs, 2 analog inputs, 1 analog output), but does not yet provide the full per-terminal connector pin inventory needed for the requested 1:1 internal/external mapping in this project state.
Layout Feasibility Check
- Board outline set to 30 x 40 mm per enclosure requirement.
- Stackup initialized as Standard 2 Layer for this passive low-speed design intent.
- Initial density check with representative connector families is critical; the selected connector framework alone exceeds the available 30 x 40 mm board area.
- This indicates that exact connector selection and placement will be mechanically constrained and must be validated against the final UniPi 1.1 pin inventory and enclosure before full layout completion.
Current Project Framework Added
- JATX1: ATX 24-pin power entry header family selected.
- JTX1: 2-pole 3.81 mm field connector family selected.
- JRX1: 4-pole 3.81 mm field connector family selected.
- JUNI2: 2-pole 5.08 mm internal connector family selected.
- JUNI4: 4-pole 5.08 mm internal connector family selected.
- RLINK12, RLINK5, RLINK33: configurable 0-ohm forwarding links for 12V, 5V, and 3.3V.
Power Jumper Designator Convention
- SolderJumper 2 Open components are now named by their source voltage rail instead of generic JP numbering.
- Naming convention:
+12_Nfor +12 V source jumpers,+5V_Nfor +5 V source jumpers, and+3.3V_Nfor +3.3 V source jumpers. - Sequential numbering is unique within each voltage group.
- Current verified jumper groups:
+12_1through+12_10,+5V_1through+5V_9, and+3.3V_1through+3.3V_9. - The rename was designator-only; the existing SolderJumper 2 Open component properties and schematic net connections were preserved.
Architecture
Mapping Assumptions In Force
Open Dependency
Layout Feasibility Check
Current Project Framework Added
Power Jumper Designator Convention
