10

0

{"design_rule_check_manufacture_part_number": []}

{"decoupling_caps":[],"resistor_power_rating":[],"pull_up_pull_down":[],"capacitor_voltage_rating":[],"parts_available":[]}

0

Bare metal

{"design_rule_check_airwires":[],"design_rule_check_floating_copper":[],"design_rule_check_overlapping_copper":[],"design_rule_check_missing_footprints":[],"design_rule_check_invalid_layer":[],"design_rule_check_overlapping_fills":[],"design_rule_check_deprecated_rules":[],"design_rule_check_trace_corner_radius":[],"design_rule_check_protected_intrusions":[]}

0

0

0

[]

Consumer Electronics

0

USB

WiFi, Bluetooth

0

0

No design_rule_check_manufacture_part_number issues remain; all generic resistors, capacitors, and test points have been replaced with stocked MPN parts and the MPN DRC is clean.

0

Low-Power USB‑C Environmental Temperature & Humidity Sensor Node with Protected 5V→3.3V Supply and Dual Wi‑Fi/BLE Connectivity

Replaced R1, R2 with Yageo RC0603FR-074K7L (4.7 kΩ, 0603, 1%); replaced R3, R4 with Yageo RC0603FR-075K1L (5.1 kΩ, 0603, 1%); replaced C1–C6 with Samsung CL10B104KB8NNNC (100 nF, 50 V, X7R, 0603); replaced C7, C8 with Murata GRM21BR61C106KE15L (10 µF, 16 V, X5R, 0805); replaced TP1, TP2 with Keystone 5015 SMD test points; replaced R5, R7 with Yageo RC0603FR-074K7L (4.7 kΩ, 0603, 1%); replaced R8, R9 with Yageo RC0603FR-075K1L (5.1 kΩ, 0603, 1%); replaced C9, C10 with Samsung CL10B104KB8NNNC (100 nF, 50 V, X7R, 0603)

0

0

{"airwires": [], "mpn_errors": []}

0

0

Replaced R1, R2, R5, R7 with Yageo RC0603FR-074K7L (4.7 kΩ, 0603, 1%); replaced R3, R4, R8, R9 with Yageo RC0603FR-075K1L (5.1 kΩ, 0603, 1%); replaced C1–C6, C9, C10 with Samsung CL10B104KB8NNNC (100 nF, 50 V, X7R, 0603); replaced C7, C8 with Murata GRM21BR61C106KE15L (10 µF, 16 V, X5R, 0805); replaced TP1, TP2 with Keystone 5015 SMD test points

0

0

Priority manual routing checklist 1) Net grouping and order - Route nets in this priority order: (1) GND, (2) 3V3, (3) 5V_PROT & USB_VBUS_IN, (4) I2C (SDA, SCL), (5) UART (UART_TX, UART_RX), (6) LED1_CTRL & LED2_CTRL and other GPIOs. - Keep each functional group physically clustered: - USB-C port & protection (J1, U1, U2, R3, R4, R5) - 5V_PROT regulator input path (U2 OUT to U3 VIN, C1, C2) - 3V3 regulator output island (U3, C7, C8, TP2, R7, C9, C10) - ESP32 module & digital I/O (U4, J2, TP1, LED1, LED2, R8, R9) - I2C sensor pod (U5, R1, R2, C10). - Keep SDA and SCL parallel and similar length from U4 to U5; likewise keep UART_TX and UART_RX roughly parallel between U4 and J2. 2) Layer usage - Use a 4-layer discipline consistent with the project intent: - L1 (Top): primary signal and short power stubs. - L2: solid GND reference plane; avoid cuts, no long signal traces. - L3: short, fat 5V_PROT and local 3V3 distribution; avoid weaving other signals in this plane. - L4 (Bottom): secondary signal escape and short jumpers only when top is congested. - When a signal must change layers, always via into L1/L4, not into the planes directly except for power stitching vias. 3) Trace widths by net type - Power nets: - USB_VBUS_IN and 5V_PROT: >= 0.50 mm on L1/L4, 0.60–0.80 mm on L3 when used as a spine. - 3V3 main rail from U3 to U4 and loads: >= 0.40 mm. - Signals: - General GPIO, LED1_CTRL, LED2_CTRL, EN: 0.20–0.25 mm. - I2C (SDA, SCL) and UART (UART_TX, UART_RX): 0.20–0.25 mm, matched width within each bus. - Local stubs into small 0603 passives may neck down briefly to 0.18 mm if needed for pad entry. 4) Via rules - Standard signal via: finished drill ~0.30 mm, pad ~0.60 mm; use for SDA, SCL, UART, GPIO, LED nets. - Power via: use at least one via pair (or via array) for each transition of USB_VBUS_IN, 5V_PROT, and 3V3 between planes; where space allows, double up vias near U3, U4 supply pins, and test points TP1/TP2. - Keep vias out of the keepout/antenna zone of the ESP32 module and away from USB-C pads and differential pairs. 5) Clearance practices - Global minimum copper clearance: >= 0.20 mm between unrelated nets. - Around USB_VBUS_IN and 5V_PROT: - Maintain >= 0.25 mm clearance to signals and other copper when possible. - Around the ESP32 and RF keepout: - Avoid routing any non-essential traces under the module antenna area; keep at least 1.0 mm away from the antenna outline. - Keep parallel high-level signals (UART, I2C) at least 0.30–0.50 mm away from unrelated fast edges or LED current paths to reduce coupling. 6) Airwire resolution workflow - For each airwire in the DRC list: - Confirm the net name (USB_VBUS_IN, 5V_PROT, 3V3, SDA, SCL, UART_TX, UART_RX, LED1_CTRL, LED2_CTRL, GND, etc.). - Route from source pin to destination along the priority and layer rules above. - Prefer straight or gently bending (45°) segments; avoid acute angles and jogs. - If a via is required, place it near the pad, not mid-span. - After each batch of routed nets, re-run DRC and verify the airwire count is decreasing; continue until all are cleared. 7) Final verification - Ensure every power pin of U3, U4, and U5 has a short, direct connection to its local decoupling capacitor and then to the plane. - Confirm no stubs or islands of copper remain on GND or 3V3/5V_PROT. - Run full DRC and verify: 0 airwires, no clearance violations, and all vias/traces on valid layers.