The focused connector correction and populated native re-export batch is completed. Actual named KiCad pads, STEP drilled holes and PH shafts now agree; the previous 1.1 mm row mismatch is resolved. These are usable, mechanically provisional integration artifacts, NOT a fabrication release or a certified 1.6 mm carrier-fit gauge. Overall Mini Muse acceptance remains separate.

This handoff supersedes the earlier R0/component plus model-only R180 compensation, earlier export links and revision e17cc530, and the earlier diagnosis that native KiCad/STEP could not satisfy the approved connector orientation. Bottom layout_2d projection is misleading; do not rotate J1 back to match that SVG. Final native KiCad/STEP geometry is the orientation authority.

Local U right, V up, W through board. J1 mates −W; LED faces +W, mapping to world −Y with approved parent transform P=(0,−18.8,96)+(u,−w,v), Rx90°. Intended nominal top datum W0 and substrate W−1.6…0 remain the construction contract, not a claim about export thickness.

Successive physical connector pitch is(−2,0) mm locally, matching approved world pitch(−2,0,0). With the intended nominal Bottom W−1.6 reference, pin1 world position remains(1,−17.2,95.05); the actual exported mounting plane is separately disclosed below. J1 body remains centered U0,V−1.5 and its original model is retained.

Source layout revision 93c9a7b9, 2026-10-04T23:10:47.263Z. Later evidence/file additions do not change this exported layout.

STEP SHA256: 830775e607ccc2eecdde53a757d07597ccd6f2a58fd1c0940994c0426ab17783. GLB SHA256: 376413df16f6157eaabbf700f01e716e44e2fa70bed2b6d575057bb8bc2e6a05. Native KiCad SHA256: 341000e51a98dc5cd67f039c979aa2079464879261946a494f3981f7b92280f9.

Earlier diagnostic STEP/GLB/scene and indicator-cad-evidence.json remain historical evidence only; do not use them for current placement.

STEP units are millimeters, Z-up. Board slab bounds X10…22, Y−20…−10, Z0…1.410; XY center(16,−15). Convert XY by u=x−16; v=y+15.

For the outer-copper top-plane convention, normalize w=z−1.445; that modeled top-plane center is(16,−15,1.445). If using slab-top datum, normalize w=z−1.410 and explicitly label it slab-top. LED seat1.495 is neither slab top nor outer-copper top: never silently use a component seat as the board surface. Under outer-copper normalization the LED seat is W+0.050 and the PH mount node is W−1.530, not nominal W−1.600. The PH source has an additional0.003 mm modeled housing offset relative to its mount node.

GLB units are meters, Y-up; mapping from STEP is GLB=(STEP x, STEP z, −STEP y)×0.001. Recover STEP millimeters with (x,y,z)=1000*(GLB X,−GLB Z,GLB Y), then normalize using the declared plane. Slab-top center GLB=(0.016,0.001410,0.015); outer-copper-top center=(0.016,0.001445,0.015).

Independent OpenCascade Boolean tests on the final STEP: LED/slab=0, PH/slab=0, LED/PH=0 mm³. Shafts sectioned at Z2.000 are0.5 mm square and centered(15,−15.95),(17,−15.95), matching Ø0.8 drilled holes and actual pin/net identities. Delivered lead/hole tolerances and solder geometry are not certified by nominal CAD.

Source physical settings remain Top mask0.015 / Top copper0.035 / FR4 core1.500 / Bottom copper0.035 / Bottom mask0.015 mm, nominal sum1.600. Paste/overlay carriers are zero thickness. Through-via configuration L1→L2 is0.4 mm drill/0.8 mm land. FR4 Dk4.3 remains provisional; no controlled-impedance requirement applies.

Native KiCad thickness field is1.500 mm, exported STEP slab1.410, GLB outer-copper span1.480, outer-mask span1.510, and component-node mounting separation1.580 mm. These measured differences remain a dimensional qualification blocker, not permission to inflate a mesh, change the approved finished thickness or certify precise1.6 mm edge-retainer fit. Parent integration may use the aligned provisional export only with its selected datum and this discrepancy explicit.

Inherited wrong LED model and fabrication sketch are locally suppressed; correct vendor model is separately parented under LED1. Final exports exclude HSMA-C190. Existing label overrides remain; native rendering/export still appears to retain some Bottom silk on Top. Neither issue justifies circuit or optical-datum changes in this batch.

Final native review 2026-10-04T23:17:07.495Z: Error LED_ANODE airwire; Error LED1 Components Outside Board; Warning two A/K component-owned land overrides; Info four model/fabrication/reference overrides. No ERC, schematic-legibility, overlapping-copper, missing-footprint, invalid-layer, stackup-validation, body-overlap or keepout findings were returned. An Error remains wrong/unresolved; the independent bounds observation is not a waiver or assertion that the check passed. Warnings remain possibly wrong/reviewable, and Info remains noteworthy rather than an automatic failure.

Optical approved nominal gap remains0.25 mm and only0.10 mm at the1.10 mm LED maximum-height envelope before solder/assembly tolerances; export plane reconciliation adds an explicit integration concern. No lightpipe fit, retained-light material, uniform illumination, mated-plug latch/crimp exit,10 mm service stroke,2 mm tail/solder reserve or edge-capture retention acceptance is claimed. Parent connectors/exterior and mainboard current limiting are unchanged.

Next safe lead action: use only these current aligned exports for provisional parent integration with a declared top-plane convention; keep the thickness discrepancy and persistent placement Error open. Precise optical/retainer fit, routing and fabrication release require separate authorized verification stages. No further connector rotation loop or rollback is needed: the focused R180 approach passed actual pin/drill/shaft registration.