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MotoCluster RevA Design Notes
- Project: EV motorcycle instrument cluster.
- Power entry block uses +12V_IN and +12V_PROT rails.
- Standing rules and locked pin assignments are maintained as project knowledge.
- Added power conversion and supervision subsystem:
- TPS54331 buck from +12V_PROT to +5V_SYS
- AMS1117-3.3 from +5V_SYS to +3V3_DIG
- Ferrite-bead filtered +3V3_ANA rail from +3V3_DIG
- Ferrite-bead filtered +VDDA rail from +3V3_ANA
- Reset supervisor on +3V3_DIG with nRESET
- AGND is kept separate from GND except at the C_LDO_OUT negative terminal star point.
- Exact requested rail names in use: +12V_PROT, +5V_SYS, +3V3_DIG, +3V3_ANA, +VDDA, GND, AGND, nRESET, VREF+.
- Requested library gaps were handled by preserving the requested MPNs in component metadata where exact library coverage was unavailable.
- STM32 integration decisions:
- MCU is STM32H747IIT6 in LQFP-176 only.
- Locked user pin assignments are preserved for SWD, USB, LSE, PC13 reserved, LCD, CAN, SPI4 flash, ADC inputs, digital inputs, LEDs, buzzer, and I2C1.
- HSE uses ABM8 25 MHz crystal and LSE uses FC-135R 32.768 kHz family crystal.
- The exact requested PRPC004SFAN-RC I2C header was not available in library coverage, so a standard 1x4 header is used while preserving the requested MPN in metadata.
- Display and backlight integration notes:
- J_DISP uses Hirose FH12-30S-0.5SH(55) as the 30-pin 0.5 mm FPC connector.
- Required schematic/layout note near the display connector: "DSI DIFF: 100 ohm, matched, no vias".
- Required schematic/layout note near the boost section: "TPS61165 boost - tight switching loop on PCB".
- LQFP-176 package limitation: STM32H747IIT6 exposes DSI_D0P, DSI_D0N, DSI_CKP, and DSI_CKN, but does not expose DSI_D1P or DSI_D1N in this package.
- Locked nets confirmed before display integration: LCD_RST on PG0, DSI_TE on PE0, LCD_BL_EN on PD13.
- LCD_BL_PWM remains unresolved on the present MCU symbol because the requested PJ12 pin is not exposed on the current LQFP-176 symbol.
- Preserve exact DSI pair naming with _P/_N suffixes for future layout constraints and export workflows.
- CAN integration notes:
- Added U_CAN as TJA1050T/CM,118 on +5V_SYS.
- CAN1_TX is wired on U_MCU PD1 and CAN1_RX is wired on U_MCU PD0.
- Added local 100nF decoupling capacitor C_CAN1 from +5V_SYS to GND at the transceiver.
- Added common-mode choke L_CMC_CAN in series with CANH and CANL.
- Added D_CAN as connector-side TVS/ESD protection across the post-choke CAN differential pair.
- Added J_CAN as a signal-only 3-pin JST XH connector: pin 1 = CANH, pin 2 = CANL, pin 3 = GND, with no VCC connection.
- Exact requested Murata ACM2012-900-2P-T002 was unavailable in the library, so CM3440Z171R-10 was used as the available 2-line common-mode choke substitute.
- USB charging and output integration notes:
- Added J_USBC as UJ20-C-H-G-SMT-2-P16-TR USB-C receptacle.
- Added 5.1k CC pull-downs R_CC1 and R_CC2 to advertise USB-C sink/UFP behavior.
- Added U_ESD as PRTR5V0U2X,215 to clamp USB_DM and USB_DP, with VCC tied to +5V_SYS and GND to system ground.
- Wired USB_DP to U_MCU PA12 and USB_DM to U_MCU PA11.
- Added U_CHG as IP5306 with VIN and VOUT tied to +5V_SYS, BAT broken out on VBAT_CHG, and SW broken out on IP5306_SW.
- Added C_CHG_IN = 10uF on VIN and C_BAT_CHG/C_VOUT1/C_VOUT2 = 22uF bulk capacitors on BAT/VOUT rails.
- Added L_CHG = 1uH on the IP5306 SW node, but its far end is intentionally left no-connect for now because the exact boost topology completion around the chosen library symbol still needs follow-up validation against the full reference application.
- Added J_USBA as a USB-A output connector tied to +5V_SYS and GND; D+ and D- are not yet given a dedicated charging-signature network.
- Current implementation preserves the requested +5V_SYS rail and USB data access, but the battery connector and any charge-identification resistor network for USB-A remain to be added in a later pass if needed.
- HMI and debug access notes:
- Added three status LEDs D10/D11/D12 with 620 ohm series resistors R19/R20/R21 from +3V3_DIG and low-side MCU drive.
- Added buzzer BZ1 with low-side NPN driver Q1 and base resistor R22.
- Added remaining Keystone 5015 debug test points TP6-TP11 for GND, AGND, CAN1_TX, CAN1_RX, USB_DP, and USB_DM.
- Current project MCU symbol does not expose the originally requested PI12/PI13/PI14/PH13 pin names. The implemented accessible pins used for this block are PB12, PB13, PB14, and PD12, while the intended logical names are preserved in the HMI net labels PI12, PI13, PI14, and BUZZER_EN for later firmware mapping review.
