ESP32-S3 System Design Inquiry

Thought for 2 mins 46 sec

You’re right. Many of the decoupling capacitors I added as placeholders were never wired. Here’s the current state and how I’ll fix it.

What’s unconnected now

Unconnected caps: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12.
Connected rail caps (ok): SYS bulk/decoupling C13, C14; 3.3 V bulk/decoupling C15, C16.
Relevant ICs and rails: charger U1 (SYS), buck‑boost U2 (3.3 V), fuel gauge U3, MCU U4, camera U5, display U6, test points TP1/TP2/TP3/TP4, Tag‑Connect J4, duplicate Tag‑Connect J5.

Why this happened

I placed a decoupling/bulk “budget” up front and only tied the main rail caps. The per‑IC local 100 nF caps were not yet wired to each IC’s power pin/GND.

Recommended decoupling cleanup (concise and cost‑effective)

Keep rail decoupling as placed:
- SYS (U1 OUT): [C13] 100 nF + [C14] 10 µF to GND.
- 3.3 V (U2 VOUT): [C15] 100 nF + [C16] 10 µF to GND.
Add one local 100 nF at each powered IC and module:
- [U4] ESP32 3.3 V: wire one of [C7]/[C8] to 3.3 V and GND near VDD3P3 pins.
- [U5] OV2640 3.3 V: wire one of [C9]/[C10] to 3.3 V and GND near pin 1.
- [U6] ST7789 3.3 V: wire one of [C11]/[C12] to 3.3 V and GND near 3V.
- [U3] MAX17055: wire one of [C5]/[C6] (100 nF) from its 3.3 V pin to GND.
Remove the rest of the unused capacitors to avoid clutter and confusion.

Notes from best practices I’ll follow

Use a typical combo of 100 nF + 1 µF + 10 µF to cover high and low frequencies where needed, prioritizing the 100 nF right at the IC pin, with larger values nearby.
Ensure capacitor voltage ratings run at no more than 60% of their maximum rated voltage.

Want me to fix it now?

I can wire: C7/C8→[U4] 3.3 V, C9/C10→[U5] 3.3 V, C11/C12→[U6] 3.3 V, C5/C6→[U3] 3.3 V; keep [C13]–[C16] as rail decoupling; delete the extra unused caps; and also remove the duplicate Tag‑Connect J5.
Confirm and I’ll apply these connections and cleanups in one pass.

generalquin

U2 is not fully connected too， hmmm....

Thought for 2 mins 24 sec

flux

You’re right: U2 isn’t fully wired. I’ve prepared a fix plan to complete it and correct the power nets.

Planned changes:

Correct SYS path: keep U7:BAT→U1:IN only; isolate U1:OUT as SYS feeding U2:VIN.
Finish U2: add inductor between its switch pins, FB divider for 3.3 V, tie EN to SYS, set PS/SYNC, add PG pull-up, complete AGND/PGND, and place 100 nF + 10 µF on VIN and VOUT.
Reconnect 3.3 V from U2:VOUT to all loads: U4, U5, U6, U3, and test points.
Decoupling cleanup: keep rail bulk caps, add one 100 nF local at each IC, remove stray unused caps. Then run ERC.

Click Start on the plan bar and I’ll execute these fixes.

Select inductor

Calculate FB resistors

Determine pull-up values

Advise cap placement

Define net classes

Started implementing a plan

#Goal

- Fully connect the TPS63020 (U2) buck-boost converter and correct the surrounding power paths to ensure that the 3.3V rail is valid, stable, and reliable for all connected loads in the ESP32-S3-PICO-N2R8 Qi-powered camera system.

#Implementation plan

1. Correct Power Path Nets

1. Disconnect SYS from U1:IN and keep U7:BAT feeding only U1:IN.

2. Isolate U1:OUT as the SYS rail and verify that it exclusively feeds U2:VIN.

2. Fully Connect U2 (TPS63020) per the Datasheet

1. Add the inductor between the appropriate pins (L1/L2) as recommended.

2. Implement the feedback (FB) divider circuit to generate the 3.3V output from U2:VOUT.

3. Tie U2:EN to the SYS rail with an appropriate pull-up resistor.

4. Configure the PS/SYNC and PG pins of U2: ensure a pull-up is added on PG.

5. Connect AGND and PGND appropriately.

6. Place decoupling capacitors (100 nF and 10 µF) at VIN and VOUT for proper regulation and noise suppression; also ensure any additional VINA decoupling per datasheet guidance.

3. Distribute the 3.3V Rail

1. Connect U2:VOUT to the rest of the loads including U4 (ESP32-PICO-D4), U5 (OV2640), U6 (Adafruit ST7789 TFT), U3 (MAX17055), pull-ups, and test points.

4. Clean Decoupling and Unused Components

1. Place a local 100 nF capacitor at each critical IC (ESP32, OV2640, ST7789, MAX17055).

2. Retain the bulk rail decoupling capacitors as needed and remove any stray or unused capacitors (C1–C12) that are not correctly connected.

5. Final ERC and Schematic Verification

1. Review the schematic ensuring all non-connected pins on U2 and other ICs are correctly connected.

2. Run ERC to confirm that there are no errors and that the complete power network is compliant with design guidelines.

#Success criteria

- The TPS63020 (U2) is fully connected per its datasheet recommendations including proper inductor, FB divider, EN, PG, and PS/SYNC connections with appropriate decoupling.

- The power path is corrected so that the SYS rail (U1:OUT) exclusively feeds U2:VIN and supplies 3.3V to U4, U5, U6, U3, and associated test points, with no accidental ties to U1:IN.

- The decoupling scheme is optimal with local caps at each IC and no stray unused components.

- Electrical Rule Check (ERC) passes with no errors related to U2 and power nets.

Started implementing a plan

#Goal

#Implementation plan

1. Correct Power Path Nets

1. Disconnect SYS from U1:IN and keep U7:BAT feeding only U1:IN.

2. Isolate U1:OUT as the SYS rail and verify that it exclusively feeds U2:VIN.

2. Fully Connect U2 (TPS63020) per the Datasheet

1. Add the inductor between the appropriate pins (L1/L2) as recommended.

2. Implement the feedback (FB) divider circuit to generate the 3.3V output from U2:VOUT.

3. Tie U2:EN to the SYS rail with an appropriate pull-up resistor.

4. Configure the PS/SYNC and PG pins of U2: ensure a pull-up is added on PG.

5. Connect AGND and PGND appropriately.

6. Place decoupling capacitors (100 nF and 10 µF) at VIN and VOUT for proper regulation and noise suppression; also ensure any additional VINA decoupling per datasheet guidance.

3. Distribute the 3.3V Rail

1. Connect U2:VOUT to the rest of the loads including U4 (ESP32-PICO-D4), U5 (OV2640), U6 (Adafruit ST7789 TFT), U3 (MAX17055), pull-ups, and test points.

4. Clean Decoupling and Unused Components

1. Place a local 100 nF capacitor at each critical IC (ESP32, OV2640, ST7789, MAX17055).

2. Retain the bulk rail decoupling capacitors as needed and remove any stray or unused capacitors (C1–C12) that are not correctly connected.

5. Final ERC and Schematic Verification

1. Review the schematic ensuring all non-connected pins on U2 and other ICs are correctly connected.

2. Run ERC to confirm that there are no errors and that the complete power network is compliant with design guidelines.

#Success criteria

- The TPS63020 (U2) is fully connected per its datasheet recommendations including proper inductor, FB divider, EN, PG, and PS/SYNC connections with appropriate decoupling.

- The power path is corrected so that the SYS rail (U1:OUT) exclusively feeds U2:VIN and supplies 3.3V to U4, U5, U6, U3, and associated test points, with no accidental ties to U1:IN.

- The decoupling scheme is optimal with local caps at each IC and no stray unused components.

- Electrical Rule Check (ERC) passes with no errors related to U2 and power nets.

Accessing knowledge...

U4 IO23 - U5 D5

J1 PIN1 - U1 BAT

U2 VOS - U5 3.3V

U4 IO26 - U5 D7

U2 VOS - U5 3.3V

U4 IO0 - R2 P1

U4 IO16 - U5 HREF

U4 IO25 - U5 D6

U1 OUT - U2 PVIN

U4 IO0 - R2 P1

U1 VSS - U2 AGND

U4 IO4 - U5 XCLK

U4 IO13 - U5 SIOC

U2 VOS - U5 3.3V

U4 IO32 - U5 D9

U4 IO0 - R2 P1

U4 IO25 - U5 D6

U1 OUT - U2 PVIN

U4 IO0 - R2 P1

U1 VSS - U2 AGND

U2 VOS - U5 3.3V

U4 IO17 - U6 RST

U4 IO19 - U5 D2

U4 IO2 - S1 P1

U4 IO27 - U5 D8

U4 IO17 - U6 RST

U4 IO21 - U5 D3

U2 VOS - U5 3.3V

U1 VSS - U2 AGND

U1 OUT - U2 PVIN

U4 IO18 - U6 SCK

U4 IO0 - R2 P1

U2 VOS - U5 3.3V

U4 IO13 - U5 SIOC

U2 VOS - U5 3.3V

U1 VSS - U2 AGND

U4 IO22 - U5 D4

U4 IO26 - U5 D7

U4 IO0 - R2 P1

U2 VOS - U5 3.3V

U4 IO12 - U5 SIOD

U4 IO2 - S1 P1

U1 VSS - U2 AGND

U4 IO16 - U5 HREF

U4 IO14 - U5 PCLK

U4 IO13 - U5 SIOC

U4 IO4 - U5 XCLK

U4 IO12 - U5 SIOD

U1 OUT - U2 PVIN

U4 IO19 - U5 D2

U4 IO22 - U5 D4

U2 VOS - U5 3.3V

U4 IO15 - U5 VSYNK

J1 PIN1 - U1 BAT

U2 VOS - U5 3.3V

U4 IO23 - U5 D5

U2 VOS - U5 3.3V

U4 IO23 - U5 D5

U1 OUT - U2 PVIN

U4 IO16 - U5 HREF

U4 IO27 - U5 D8

U1 VSS - U2 AGND

U2 VOS - U5 3.3V

U1 VSS - U2 AGND

U4 IO0 - R2 P1

U4 IO15 - U5 VSYNK

U4 IO12 - U5 SIOD

U2 VOS - U5 3.3V

U1 VSS - U2 AGND

U4 IO12 - U5 SIOD

U4 IO32 - U5 D9

U2 VOS - U5 3.3V

U4 IO13 - U5 SIOC

U4 IO18 - U6 SCK

U4 IO14 - U5 PCLK

U1 VSS - U2 AGND

U4 IO5 - U6 TFTCS

U1 VSS - U2 AGND

U1 OUT - U2 PVIN

U1 VSS - U2 AGND

U4 IO0 - R2 P1

U4 IO21 - U5 D3

U4 IO13 - U5 SIOC

U4 IO12 - U5 SIOD

C16

Capacitance

Resistance

10kΩ

C12

Capacitance

C15

Capacitance

Resistance

500 Ω

Capacitance

Resistance

10kΩ

Capacitance

Resistance

500 Ω

Capacitance

C13

Capacitance

Resistance

500 Ω

C14

Capacitance

Resistance

500 Ω

Capacitance

C10

Capacitance

C11

Capacitance

TP4

TP1

TP2

TP3

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Project Name

Description

ESP32-S3-PICO-N2R8 Qi-Powered Camera Module with Buck-Boost Regulation, OV2640, ST7789 Display, Advanced Fuel Gauge, and Tag-Connect Programming

Properties

System Architecture

flowchart LR
  subgraph Power
    QiReceiver[Qi Receiver] --> Charger[BQ24075 Charger]
    Charger --> BatteryConnector[J1 Battery Connector]
    BatteryConnector --> BuckBoostIn[Battery]
    BuckBoostIn --> BuckBoost[TPS63020 Buck-Boost]
    BuckBoost --> Rail3v3[3.3V Rail]
  end

  subgraph MCU
    Rail3v3 --> MCU[ESP32-PICO-D4 MCU]
    MCU --> Camera[OV2640 Camera]
    MCU --> Display[ST7789 Display]
    MCU --> FuelGauge[Fuel Gauge]
    MCU --> Button[User Button]
    MCU --> LED[User LED]
  end

  subgraph Programming
    MCU --> TagConnect[Tag-Connect TC2030]
    TagConnect --> U0TXD[U0TXD]
    TagConnect --> U0RXD[U0RXD]
    TagConnect --> EN[EN]
    TagConnect --> GPIO0[GPIO0]
    TagConnect --> PWR3V3[3.3V]
    TagConnect --> GND[GND]
  end

  subgraph I2C
    Rail3v3 --> SIOD[SIOD/SDA]
    Rail3v3 --> SIOC[SIOC/SCL]
    SIOD --> Camera
    SIOC --> Camera
    SIOD --> FuelGauge
    SIOC --> FuelGauge
  end

  subgraph Testpoints
    TP1(3.3V TP) --> Rail3v3
    TP2(GND TP) --> GND
    TP3(SDA TP) --> SIOD
    TP4(SCL TP) --> SIOC
  end

Pricing & Availability

Distributor	Qty 1
Arrow	$5.87–$7.41
Digi-Key	$9.50–$14.78
LCSC	$16.76
Mouser	$20.07
TME	$23.63
Verical	$4.44–$5.87

Controls

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