generalquin

/

All changes saved

0

0

Files

Schematic

PCB

Log InSign Up

ESP32-S3 System Design Inquiry

flux

2:24

Accessing knowledge base.

You’re right: U2 isn’t fully wired. I’ve prepared a fix plan to complete it and correct the power nets.
Planned changes:
  • Correct SYS path: keep U7:BAT→U1:IN only; isolate U1:OUT as SYS feeding U2:VIN.
  • Finish U2: add inductor between its switch pins, FB divider for 3.3 V, tie EN to SYS, set PS/SYNC, add PG pull-up, complete AGND/PGND, and place 100 nF + 10 µF on VIN and VOUT.
  • Reconnect 3.3 V from U2:VOUT to all loads: U4, U5, U6, U3, and test points.
  • Decoupling cleanup: keep rail bulk caps, add one 100 nF local at each IC, remove stray unused caps. Then run ERC.
Click Start on the plan bar and I’ll execute these fixes.
Plan
#Goal
  • Fully connect the TPS63020 (U2) buck-boost converter and correct the surrounding power paths to ensure that the 3.3V rail is valid, stable, and reliable for all connected loads in the ESP32-S3-PICO-N2R8 Qi-powered camera system.
#Implementation plan
  1. Correct Power Path Nets
    1. Disconnect SYS from U1:IN and keep U7:BAT feeding only U1:IN.
    2. Isolate U1:OUT as the SYS rail and verify that it exclusively feeds U2:VIN.
  2. Fully Connect U2 (TPS63020) per the Datasheet
    1. Add the inductor between the appropriate pins (L1/L2) as recommended.
    2. Implement the feedback (FB) divider circuit to generate the 3.3V output from U2:VOUT.
    3. Tie U2:EN to the SYS rail with an appropriate pull-up resistor.
    4. Configure the PS/SYNC and PG pins of U2: ensure a pull-up is added on PG.
    5. Connect AGND and PGND appropriately.
    6. Place decoupling capacitors (100 nF and 10 µF) at VIN and VOUT for proper regulation and noise suppression; also ensure any additional VINA decoupling per datasheet guidance.
  3. Distribute the 3.3V Rail
    1. Connect U2:VOUT to the rest of the loads including U4 (ESP32-PICO-D4), U5 (OV2640), U6 (Adafruit ST7789 TFT), U3 (MAX17055), pull-ups, and test points.
  4. Clean Decoupling and Unused Components
    1. Place a local 100 nF capacitor at each critical IC (ESP32, OV2640, ST7789, MAX17055).
    2. Retain the bulk rail decoupling capacitors as needed and remove any stray or unused capacitors (C1–C12) that are not correctly connected.
  5. Final ERC and Schematic Verification
    1. Review the schematic ensuring all non-connected pins on U2 and other ICs are correctly connected.
    2. Run ERC to confirm that there are no errors and that the complete power network is compliant with design guidelines.
#Success criteria
  • The TPS63020 (U2) is fully connected per its datasheet recommendations including proper inductor, FB divider, EN, PG, and PS/SYNC connections with appropriate decoupling.
  • The power path is corrected so that the SYS rail (U1:OUT) exclusively feeds U2:VIN and supplies 3.3V to U4, U5, U6, U3, and associated test points, with no accidental ties to U1:IN.
  • The decoupling scheme is optimal with local caps at each IC and no stray unused components.
  • Electrical Rule Check (ERC) passes with no errors related to U2 and power nets.
Select inductor
Calculate FB resistors
Determine pull-up values
Advise cap placement
Define net classes
204 days

Started implementing a plan

#Goal

- Fully connect the TPS63020 (U2) buck-boost converter and correct the surrounding power paths to ensure that the 3.3V rail is valid, stable, and reliable for all connected loads in the ESP32-S3-PICO-N2R8 Qi-powered camera system.

#Implementation plan

1. Correct Power Path Nets

1. Disconnect SYS from U1:IN and keep U7:BAT feeding only U1:IN.

2. Isolate U1:OUT as the SYS rail and verify that it exclusively feeds U2:VIN.

2. Fully Connect U2 (TPS63020) per the Datasheet

1. Add the inductor between the appropriate pins (L1/L2) as recommended.

2. Implement the feedback (FB) divider circuit to generate the 3.3V output from U2:VOUT.

3. Tie U2:EN to the SYS rail with an appropriate pull-up resistor.

4. Configure the PS/SYNC and PG pins of U2: ensure a pull-up is added on PG.

5. Connect AGND and PGND appropriately.

6. Place decoupling capacitors (100 nF and 10 µF) at VIN and VOUT for proper regulation and noise suppression; also ensure any additional VINA decoupling per datasheet guidance.

3. Distribute the 3.3V Rail

1. Connect U2:VOUT to the rest of the loads including U4 (ESP32-PICO-D4), U5 (OV2640), U6 (Adafruit ST7789 TFT), U3 (MAX17055), pull-ups, and test points.

4. Clean Decoupling and Unused Components

1. Place a local 100 nF capacitor at each critical IC (ESP32, OV2640, ST7789, MAX17055).

2. Retain the bulk rail decoupling capacitors as needed and remove any stray or unused capacitors (C1–C12) that are not correctly connected.

5. Final ERC and Schematic Verification

1. Review the schematic ensuring all non-connected pins on U2 and other ICs are correctly connected.

2. Run ERC to confirm that there are no errors and that the complete power network is compliant with design guidelines.

#Success criteria

- The TPS63020 (U2) is fully connected per its datasheet recommendations including proper inductor, FB divider, EN, PG, and PS/SYNC connections with appropriate decoupling.

- The power path is corrected so that the SYS rail (U1:OUT) exclusively feeds U2:VIN and supplies 3.3V to U4, U5, U6, U3, and associated test points, with no accidental ties to U1:IN.

- The decoupling scheme is optimal with local caps at each IC and no stray unused components.

- Electrical Rule Check (ERC) passes with no errors related to U2 and power nets.

204 days

Started implementing a plan

#Goal

- Fully connect the TPS63020 (U2) buck-boost converter and correct the surrounding power paths to ensure that the 3.3V rail is valid, stable, and reliable for all connected loads in the ESP32-S3-PICO-N2R8 Qi-powered camera system.

#Implementation plan

1. Correct Power Path Nets

1. Disconnect SYS from U1:IN and keep U7:BAT feeding only U1:IN.

2. Isolate U1:OUT as the SYS rail and verify that it exclusively feeds U2:VIN.

2. Fully Connect U2 (TPS63020) per the Datasheet

1. Add the inductor between the appropriate pins (L1/L2) as recommended.

2. Implement the feedback (FB) divider circuit to generate the 3.3V output from U2:VOUT.

3. Tie U2:EN to the SYS rail with an appropriate pull-up resistor.

4. Configure the PS/SYNC and PG pins of U2: ensure a pull-up is added on PG.

5. Connect AGND and PGND appropriately.

6. Place decoupling capacitors (100 nF and 10 µF) at VIN and VOUT for proper regulation and noise suppression; also ensure any additional VINA decoupling per datasheet guidance.

3. Distribute the 3.3V Rail

1. Connect U2:VOUT to the rest of the loads including U4 (ESP32-PICO-D4), U5 (OV2640), U6 (Adafruit ST7789 TFT), U3 (MAX17055), pull-ups, and test points.

4. Clean Decoupling and Unused Components

1. Place a local 100 nF capacitor at each critical IC (ESP32, OV2640, ST7789, MAX17055).

2. Retain the bulk rail decoupling capacitors as needed and remove any stray or unused capacitors (C1–C12) that are not correctly connected.

5. Final ERC and Schematic Verification

1. Review the schematic ensuring all non-connected pins on U2 and other ICs are correctly connected.

2. Run ERC to confirm that there are no errors and that the complete power network is compliant with design guidelines.

#Success criteria

- The TPS63020 (U2) is fully connected per its datasheet recommendations including proper inductor, FB divider, EN, PG, and PS/SYNC connections with appropriate decoupling.

- The power path is corrected so that the SYS rail (U1:OUT) exclusively feeds U2:VIN and supplies 3.3V to U4, U5, U6, U3, and associated test points, with no accidental ties to U1:IN.

- The decoupling scheme is optimal with local caps at each IC and no stray unused components.

- Electrical Rule Check (ERC) passes with no errors related to U2 and power nets.

204 days

Working...


​
Sign up to send

To get started, talk to Flux or create a New Document.

Reviews

Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    Assets are files uploaded to this project which can be used in various ways.

    Patient Amber Heat-Ray thumbnail
    ESP32-S3-PICO-N2R8 Qi-Powered Camera Module with Buck-Boost Regulation, OV2640, ST7789 Display, Advanced Fuel Gauge, and Tag-Connect Programming

    Properties

    flowchart LR
      subgraph Power
        QiReceiver[Qi Receiver] --> Charger[BQ24075 Charger]
        Charger --> BatteryConnector[J1 Battery Connector]
        BatteryConnector --> BuckBoostIn[Battery]
        BuckBoostIn --> BuckBoost[TPS63020 Buck-Boost]
        BuckBoost --> Rail3v3[3.3V Rail]
      end
    
      subgraph MCU
        Rail3v3 --> MCU[ESP32-PICO-D4 MCU]
        MCU --> Camera[OV2640 Camera]
        MCU --> Display[ST7789 Display]
        MCU --> FuelGauge[Fuel Gauge]
        MCU --> Button[User Button]
        MCU --> LED[User LED]
      end
    
      subgraph Programming
        MCU --> TagConnect[Tag-Connect TC2030]
        TagConnect --> U0TXD[U0TXD]
        TagConnect --> U0RXD[U0RXD]
        TagConnect --> EN[EN]
        TagConnect --> GPIO0[GPIO0]
        TagConnect --> PWR3V3[3.3V]
        TagConnect --> GND[GND]
      end
    
      subgraph I2C
        Rail3v3 --> SIOD[SIOD/SDA]
        Rail3v3 --> SIOC[SIOC/SCL]
        SIOD --> Camera
        SIOC --> Camera
        SIOD --> FuelGauge
        SIOC --> FuelGauge
      end
    
      subgraph Testpoints
        TP1(3.3V TP) --> Rail3v3
        TP2(GND TP) --> GND
        TP3(SDA TP) --> SIOD
        TP4(SCL TP) --> SIOC
      end
    

    Pricing & Availability

    Distributor

    Qty 1

    Arrow

    $5.87–$7.41

    Digi-Key

    $9.50–$14.78

    LCSC

    $16.76

    Mouser

    $20.07

    TME

    $23.63

    Verical

    $4.44–$5.87

    Controls

    Welcome 👋

    Flux helps you build PCBs faster with an AI teammate!

    Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.

        Introducing AI Placement!
        AI Placement Demo

        AI-Powered Component Placement

        Let AI place your components intelligently. AI Placement analyzes your schematic and positions components for optimal routing, signal integrity, and board density.

        From Schematic to Layout in Seconds

        Skip the tedious manual placement. AI Placement generates a starting layout you can refine, saving hours of repetitive work on every new design.

        Works With Auto-Layout

        Pair AI Placement with Auto-Layout for a complete AI-driven PCB design flow — from component placement through trace routing, all with one click.

        Try it