Fixing Airwire Errors

flux

The stale marker changed to another local 5V_PROT trace segment (Trace 1322), still tied to C1:P1. I’m cleaning that local segment and re-checking again.

flux

After removing the stale local segments, DRC now exposes two short 5V_PROT airwires and the board pre-check says routing is feasible. I’m running a focused routing cleanup pass now.

flux

The C1 airwire is cleared, but the cleanup route introduced overlapping-copper DRC errors. I’m removing the offending cleanup traces/vias so we don’t leave the board with shorts, then I’ll re-check DRC.

flux

The cleanup removed the shorts, but it opened several small local airwires/dangling traces. The board check says routing is feasible, but another route pass may introduce new conflicts; I’m stopping here rather than risking further churn.

flux

I reworked the local C1:P1 / 5V_PROT routing and re-ran DRC. The original C1:P1 airwire was removed, but the repair route introduced other local routing issues; I removed the shorting overlaps, and the latest DRC now shows 4 airwires and 3 dangling-trace warnings, with no overlapping-copper errors in the checked set.
So the board is still not export-ready. The next safe step is a careful manual PCB edit around the affected traces rather than another blind autoroute pass, because the router is now creating cleanup churn.
Manual routing fix
Inspect affected nets
Revert cleanup route
Create repair plan
Check manufacturability

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LampOS RGBWW Controller PCB v1 — Project Specification
Project Overview
Production-intent compact controller PCB for Lamplit lamp bulbs running LampOS. Status: Draft requirements captured; schematic/layout implementation pending.
Intended Use
Installed inside lamp bulb assemblies for OTA-capable RGBWW lighting. Designed for JLCPCB fabrication/assembly, high-volume manufacturing, outdoor/festival reliability, and 5 V battery-pack or adapter-powered installations.
What the Device Should Do
  • Control two independent 16-LED RGBWW addressable rings.
  • Provide Wi-Fi/Bluetooth connectivity through ESP32-WROOM-32-N4.
  • Accept protected 5 V input through large solder pads.
  • Support UART pogo-pin programming plus OTA updates.
  • Fit through an approximately 2.5 inch opening.
Main Features
  • ESP32-WROOM-32-N4, JLCPCB C82899.
  • 32x SK6812RGBW-WS RGBWW LEDs, JLCPCB C5297619.
  • Two independent LED data chains: shade/top and base/bottom.
  • 5 V/3 A protected power input.
  • 3.3 V TLV75733PDBVR regulator for ESP32 and logic support.
  • 74AHCT125-class 5 V level shifting for LED data.
  • BOOT and RESET tactile switches.
  • UART programming pads and production test pads.
System Architecture
Diagram



  
    
  
  
    
  

















GPIO14

330 ohm

330 ohm













5V and GND input pads
3A PPTC fuse
AO3401A P-channel reverse polarity MOSFET
SMBJ5.0A TVS clamp
Protected node_5V rail
Top node_16x SK6812 RGBWW ring
Bottom node_16x SK6812 RGBWW ring
TLV75733PDBVR 3.3V LDO
74AHCT125 level shifter
3.3V rail
ESP32-WROOM-32-N4
UART pogo pads
BOOT and RESET buttons
Hardware Subsystems
Power Input and Protection
  • Source: 5 V DC through large solder pads, no USB-C connector on this board revision.
  • Target input capacity: 0.5 A to 3 A sources; firmware/usage must respect source capability.
  • Protection chain: 3 A PPTC, AO3401A reverse polarity protection, SMBJ5.0A transient suppression.
  • Bulk capacitance: 1000 uF preferred, 470 uF minimum near power entry.
3.3 V Regulation
  • TLV75733PDBVR 3.3 V LDO, 1 A class.
  • Include datasheet-required input and output capacitors.
  • Feeds ESP32 and 3.3 V-side logic only; LEDs remain on 5 V.
Controller and Radio
  • ESP32-WROOM-32-N4 module.
  • Antenna at PCB edge with no copper/components/LEDs below or adjacent per Espressif keepout.
  • EN pull-up and reset RC per Espressif recommendations.
  • GPIO0 boot switch to ground.
LED System
  • 16 top LEDs and 16 bottom LEDs, SK6812RGBW-WS.
  • Rings are independent and not daisy-chained together.
  • Top/shade data: ESP32 GPIO12 -> AHCT buffer -> 330 ohm -> first top DIN.
  • Bottom/base data: ESP32 GPIO14 -> AHCT buffer -> 330 ohm -> first bottom DIN.
  • Place data resistors near first LED of each chain.
Programming and Test
  • No USB connector, USB-UART bridge, or USB power circuitry on board.
  • Pogo pads: 3V3, GND, TX0, RX0, EN, GPIO0.
  • Test pads: TOP_DIN, TOP_DOUT, BOT_DIN, BOT_DOUT, 5V, GND, 3V3.
Interfaces and Connections

Table

FunctionNet / GPIONotes
Top ring dataGPIO12ESP32 strapping concern: GPIO12 must not be pulled high at boot; AHCT input should not force it high.
Bottom ring dataGPIO14LED data output.
UART TXGPIO1Programming pad TX0.
UART RXGPIO3Programming pad RX0.
BootGPIO0Button to GND and programming pad.
ResetENButton to GND and programming pad.
Power and Runtime Expectations
  • Design target: 3 A continuous input capacity.
  • Worst-case LED load: approximately 2.6 A at 5 V.
  • Expected total worst-case input: approximately 3.0 A including ESP32/logic margin.
  • Runtime is source-dependent; no onboard battery charging specified in this revision.
Power Tree and Power Budget
See power-budget project file for the detailed load table and sizing notes.
Manufacturing and Assembly Expectations
  • JLCPCB fabrication and assembly.
  • 4-layer PCB.
  • Long-term availability and production reliability are priorities.
  • Must include accessible programming and test pads.
  • Double-sided LED assembly: one ring top, one ring bottom.
Firmware-Relevant Hardware Requirements
  • LampOS firmware.
  • Initial flashing over UART; OTA thereafter.
  • Pin assignments fixed as specified.
  • Firmware should limit brightness/current based on source capability if source current cannot be detected in hardware.
Physical Design Expectations
  • Primarily circular board, max diameter 62 mm.
  • Central M4 clearance hole, 4.3 mm.
  • Reserve future-compatible center keepout for 6.5-7.0 mm hole.
  • Center keepout diameter: 12-14 mm, no copper/traces/vias/components.
  • ESP32 antenna near board edge with all-layer antenna keepout.
Important Design Decisions
  • Use ESP32-WROOM module rather than bare RF design.
  • Use true RGBWW LEDs for warm white rather than RGB-mixed white.
  • Keep LED rings independent for LampOS zone control.
  • Use AHCT level shifting from 3.3 V ESP32 signals to 5 V LED data.
  • Use solder pads rather than USB connector on this revision.
Assumptions
  • Source current capability is not automatically detected unless a future input-identification circuit is added.
  • Full-white 32-LED operation may approach the 3 A input limit; firmware current limiting is recommended.
  • The supplied KiCad archive could not be inspected through the current file reader, so this spec is derived from the text master specification.
Change Notes
  • Initial Flux project specification created from the supplied LampOS RGBWW Controller PCB v1 master design specification.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Power Input and Protection

  • 3.3 V Regulation

  • Controller and Radio

  • LED System

  • Programming and Test

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes