• Standalone replacement for a dual-camera prototype.
• Powered and controlled by an Android phone over USB-C OTG.
• Prototype/validation build, with factory programming through JTAG.
• Target output: one stitched 1280 x 480 video stream at 30 fps.

• Power from 5 V USB-C VBUS.
• Configure and capture two OV5640 camera modules.
• Accept each camera's 8-bit DVP bus, PCLK, HREF, and VSYNC.
• Generate continuous 24 MHz XCLK for both cameras.
• Stitch synchronized VGA images side-by-side with line buffering.
• Stream the result over mandatory USB 2.0 High-Speed.
• Enumerate as a UVC 1.1 device where FPGA and USB transport resources permit.
• Boot the FPGA from internal configuration flash and expose JTAG test pads.

• Gowin GW1NR-LV9QN88P FPGA.
• Two 24-pin, 0.5 mm pitch, bottom-contact FPC camera connectors.
• External USB 2.0 High-Speed ULPI PHY.
• USB-C device/UFP connector with USB 2.0 data.
• 3.3 V and 1.2 V regulated rails.
• Camera reset, power-down, clock, configuration, and optional autofocus supply control.
• ESD protection, test points, power-good/reset supervision, and debug access.

Diagram

• Use separate capture logic for each camera clock domain.
• Capture D[9:2] on the active PCLK edge, qualified by HREF and VSYNC.
• Cross clock domains through dual-clock FIFOs or line buffers; do not assume both PCLKs are phase-aligned.
• Stitch two 640 x 480 YUV422 images into one 1280 x 480 YUV422 frame.
• Line buffering can keep hardware processing latency below one frame; the earlier sub-1 ms claim remains a target to verify in RTL and memory sizing.
• Confirm the QN88 device has enough user I/O after assigning two DVP buses, ULPI, clocks, reset, JTAG, and control signals.

• Treat this pinout as module-specific and verify it against the exact purchased module drawing before schematic release.
• Use one SCCB bus per camera or an I2C/SCCB mux because identical OV5640 modules normally share the same fixed address.
• Route separate RSTB and PWDN controls so cameras can be isolated and initialized independently.
• Prefer separate filtered camera and VCM power branches. VCM power should not inject autofocus transients into FPGA I/O power.
• Add local decoupling at each FPC power pin and ESD protection only where capacitance is compatible with the signal.

• USB-C receptacle configured as a sink/device using 5.1 kohm Rd resistors on CC1 and CC2.
• External USB 2.0 High-Speed PHY connected to the FPGA through ULPI; USB3320C is a candidate, not yet a frozen selection.
• Route D+ and D- as a 90 ohm differential pair with short, symmetric routing and a continuous ground reference.
• Place low-capacitance ESD protection adjacent to the connector.
• Confirm UVC 1.1 implementation resource use, descriptors, endpoint strategy, and Android application compatibility before schematic freeze.

• Provide a low-jitter reference oscillator suitable for FPGA logic and ULPI timing.
• Generate camera XCLK at 24 MHz; separate output enables or clock buffers are preferred for debug and isolation.
• Implement deterministic power-on reset after 1.2 V and 3.3 V rails settle.
• Expose TCK, TMS, TDI, TDO, GND, and a reference voltage on accessible test pads or a compact programming connector.

• The phone is the only intended power source; no battery is required in this revision.
• Do not assume every USB-C host guarantees 500 mA before enumeration or advertises the same Type-C current. Firmware/hardware must remain within the detected/allowed source current.
• Cameras may have startup and autofocus current transients above the supplied typical estimates.

Diagram

• Use a dual buck converter rather than two LDOs unless the completed rail budget proves LDO thermal dissipation acceptable.
• TPS62420 remains a candidate subject to rail-current, sequencing, package, switching-frequency, and thermal checks.
• Double the calculated ceramic capacitance requirement when selecting MLCCs to account for DC-bias derating.
• Size protection and connectors from the final peak input current, not the typical 146 mA estimate.

1. Reduce frame rate.
2. Reduce stitched width or resolution.
3. Use a lower-bandwidth pixel format if the host supports it.
4. Add hardware MJPEG compression or select a device with a proven compressed-video path.

• Four-layer PCB.
• Recommended initial stackup: top signal/components, solid ground, power plus low-speed routing, bottom signal/components.
• Keep Layer 2 substantially continuous under USB and clock paths.
• Controlled-impedance fabrication is required for USB D+/D-.
• Use assembly-compatible fine-pitch FPC connectors and inspectable programming/test pads.
• Exact connector land patterns and board-edge locations must come from manufacturer drawings.

• Internal FPGA configuration flash boot.
• Factory JTAG programming only for the prototype phase.
• Independent camera reset and power-down control.
• Separate camera configuration paths or an address-isolation mechanism.
• UVC descriptors for a 1280 x 480 stream and negotiated fallback modes.
• Error telemetry for camera lock, FIFO overflow/underflow, USB link state, and dropped frames.

• Board outline: 40 mm x 50 mm maximum.
• FPGA central to the two camera connectors and ULPI PHY.
• PHY adjacent to USB-C; minimize ULPI and USB routing lengths.
• FPC connectors placed to match case cable exits and bottom-contact orientation.
• Regulators and inductors kept away from camera clocks, analog camera supply filtering, and USB differential routing.
• Reserve edge access for USB-C, both FPC cables, and programming fixtures.

• Use parallel DVP OV5640 modules, not direct MIPI CSI-2.
• Use an external ULPI USB 2.0 High-Speed PHY.
• Use line/FIFO buffering to handle independent camera clock domains.
• Use dual buck conversion for 3.3 V and 1.2 V pending the final budget.
• Target UVC 1.1, while treating uncompressed 1280 x 480 at 30 fps as a feasibility gate rather than a guaranteed result.

• Both modules genuinely match the supplied 24-pin pinout and contain their own sensor rail regulation.
• The module DVP outputs and control inputs are compatible with 3.3 V LVCMOS.
• D[9:2] represents the active 8-bit bus in the chosen OV5640 output mode.
• The mobile phone supports USB host mode and supplies sufficient current.
• The FPGA package and internal memory resources can support the chosen capture and buffering architecture; this requires toolchain validation.

1. Verify the exact camera module manufacturer, drawing, connector orientation, and pinout.
2. Verify GW1NR-LV9QN88P bank voltages, usable I/O count, PLLs, embedded memory, and USB/UVC RTL resource fit.
3. Build a rail-by-rail peak power budget before selecting TPS62420 or any alternative.
4. Prove sustained UVC bandwidth with protocol overhead and Android host constraints.
5. Decide whether autofocus is required; if not, leave VCM unpowered to reduce noise and load.
6. Define acceptable fallback video modes.

• USB 2.0 High-Speed isochronous cannot carry uncompressed 1280 x 480 YUV422 at 30 fps. The baseline uncompressed mode is now 15 fps; 30 fps requires compression or a revised transport.
• USB3320 adds a required 1.8 V rail. Use TPS62420 for 3.3 V and 1.2 V, plus a small 1.8 V LDO for the PHY.
• Preliminary system demand is 1.63 W typical and 2.49 W planning peak, corresponding to about 362-384 mA typical and 552-585 mA peak from 5 V depending on conversion efficiency.
• QN88P provides 71 user I/O; the conservative allocation uses about 52.
• The device has 468 Kbit BSRAM and 64 Mbit integrated PSRAM. Line and full-frame storage capacity are sufficient.
• Final FPGA logic fit, timing closure, and power remain dependent on RTL synthesis and routed activity analysis.

• Initial architecture created from the SentryCase request.
• Integrated the supplied OV5640 DVP pinout, dual VGA stitching target, UVC direction, ULPI PHY requirement, power estimates, and JTAG strategy.
• Added feasibility warnings for shared camera addresses, asynchronous PCLK domains, USB payload overhead, module-specific pinout verification, and incomplete peak power data.
• Frozen the proposed USB3320 VDD18 regulator as active TI TPS79318DBVR (200 mA, fixed 1.8 V, SOT-23-5); Flux library availability is recorded via the TPS79318-EP entry. Added capacitor, enable, thermal, headroom, startup, and sequencing requirements.
• Added an exact proposed QN88P package-pin allocation in Architecture Validation for both camera buses, ULPI, clocks, independent camera controls/SCCB, JTAG/configuration, regulator enables, power-good, and status.
• Planned all populated FPGA I/O banks at 3.3 V. The 71 user-capable pads reconcile as 58 assigned application signals, 8 deliberately reserved dedicated/configuration pads, and 5 spares; final acceptance is gated by Gowin .cst validation.

• The two attached text files agree with this specification, but neither is a manufacturer datasheet or mechanical drawing. The first contains architecture estimates; the second contains a claimed “standard OV5640” 24-pin mapping without an MPN.
• The camera electrical contract remains provisional: DVP D9..D2, PCLK/HREF/VSYNC outputs, 24 MHz XCLK input, independent SCCB, RSTB, PWDN, 3.3 V main and VCM branches. Exact module 3.3 V tolerance, current, pin numbering viewed from the contact side, and mating orientation are not confirmed.
• Hirose FH12-24S-0.5SH(55) is an active, exact 24-position 0.5 mm-pitch bottom-contact FPC connector available in Flux. It is a connector selection only and does not validate the unknown camera flex pinout.
• GW1NR-LV9QN88PC6/I5 is confirmed as a real production QN88P (QFN-88P, 0.4 mm) orderable. It is not present as a usable terminal-bearing Flux library part, so a verified import/custom real-part workflow is required before capture.
• No placeholder camera or FPGA component is authorized. Consequently schematic capture remains blocked rather than being populated with guessed symbols/footprints.
• Do not add schematic components until the exact camera module and final FPGA orderable suffix are confirmed and the proposed pin table passes Gowin constraint validation.
• The power tree is VBUS_PROTECTED -> TPS62420 (+3V3_BUCK, +1V2_FPGA) and +3V3_BUCK -> TPS79318DBVR -> +1V8_USBPHY; USB3320 VBAT remains on protected 5 V and VDDIO is 3.3 V.
• Required control nets: BUCK33_EN, BUCK12_EN, LDO18_EN, PG_3V3, PG_1V2, PG_1V8, USBPHY_RESETB, USBPHY_STATUS, CAM1_PWR_EN, CAM2_PWR_EN, VCM_PWR_EN.
• TPS79318 support: 1 uF input ceramic, 4.7 uF nominal output ceramic with >=2.2 uF effective capacitance, 10 nF BYPASS capacitor, and 100 kohm EN pull-down if FPGA-controlled.
• USB3320 VDD18 current basis is 29.4 mA typical / 44.1 mA planning peak. LDO planning dissipation is 66.15 mW and output-current utilization is 22.1%.
• Sequence: bucks up with cameras and PHY held inactive; enable 1.8 V; qualify it for at least 0.5 ms or with a supervisor; then allow 3.3 V VDDIO/release USB3320 RESETB; cameras start one at a time.
• TPS79318 has no power-good pin. PG_1V8 must come from an external supervisor or qualified timing logic.
• The complete exact pin table, bank accounting, support-component list, and tool-validation flags are maintained in Architecture Validation.