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Flipdot 6x8 Matrix Controller — Imported Specification
Purpose
ESP32-S3 SuperMini controlled 6 column x 8 row flip-dot / magnetic pixel matrix. The matrix uses 48 coil/inductor positions and 14 single-ended DRV8833 half-bridge outputs arranged as 8 row rails and 6 column rails.
Power Tree
  • USB-C 5V input net: VBUS
  • SS14 Schottky diode from VBUS to protected 5V motor rail VM_5V
  • VM_5V supplies all DRV8833 VM pins and the ESP32-S3 module 5V pin
  • VM_5V also feeds AP2112K-3.3 LDO input
  • AP2112K output net: VCC_3V3, used for logic pull-ups / enables
  • Common ground net: GND
Key Components from Uploaded BOM

Table

DesignatorsQtyPart / ValuePackage / FootprintLCSC
L1-L4848SRR4528A-100M, 10uH shielded inductorSRR4528AC7449
U1-U77DRV8833RTYR dual H-bridgeWQFN-16-EP 4x4mm P0.65C154936
U81ESP32-S3 SuperMini module via headers2x 1x8 header sockets-
U91AP2112K-3.3 LDOSOT-23-5C460340
D11SS14 Schottky diodeSMA / DO-214ACC8678
J11USB-C 6-pin receptacleTYPE-C-304-LCDC165948
C_BULK11000uF 16V electrolytic8x10mmC13585
C1-C1010100nF 50V X7R0805C49678
C11-C13310uF 16V X5R0805C15850
R1-R225.1k 1% USB-C CC pulldown0805C17749
R3110k 1% nSLEEP pullup0805C17414
R411k status LED resistor0805C17513
LED11Green LED0805C72043
SW11SMD tactile switch6x6mmC318884
H1-H221x8 female headers2.54mmC124378
Driver Mapping
  • U1: ROW0 on bridge A, ROW1 on bridge B
  • U2: ROW2 on bridge A, ROW3 on bridge B
  • U3: ROW4 on bridge A, ROW5 on bridge B
  • U4: ROW6 on bridge A, ROW7 on bridge B
  • U5: COL0 on bridge A, COL1 on bridge B
  • U6: COL2 on bridge A, COL3 on bridge B
  • U7: COL4 on bridge A, COL5 on bridge B
Each used rail connects to OUT1 of the corresponding bridge; OUT2 pins are intentionally unused/no-connect in the uploaded design.
ESP32-S3 GPIO Mapping

Table

FunctionGPIO
R0_IN1 / R0_IN21 / 2
R1_IN1 / R1_IN23 / 4
R2_IN1 / R2_IN25 / 6
R3_IN1 / R3_IN27 / 8
R4_IN1 / R4_IN29 / 10
R5_IN1 / R5_IN211 / 12
R6_IN1 / R6_IN213 / 14
R7_IN1 / R7_IN215 / 16
C0_IN1 / C0_IN217 / 18
C1_IN1 / C1_IN221 / 33
C2_IN1 / C2_IN234 / 35
C3_IN1 / C3_IN236 / 37
C4_IN1 / C4_IN238 / 39
C5_IN1 / C5_IN240 / 41
Status LED48
Matrix Netlist Rule
For every cell in row r and column c, inductor Lrc connects:
  • Pin 1 to ROWr
  • Pin 2 to COLc
Designator convention used in Flux: L1 = L00, L2 = L01, ... row-major through L48 = L75.
Layout Targets from Uploaded Workflow
  • Board: 70mm x 60mm, 2-layer FR-4
  • Top side assembly only
  • USB-C and power in top-left; ESP32 headers near USB-C
  • Column drivers above matrix; row drivers beside matrix
  • Matrix inductors placed as 6 x 8 array at 6.0mm x 5.0mm pitch
  • VM_5V trunk: 30 mil; matrix rails: 20 mil; GPIO: 8 mil
  • Bottom layer mostly GND pour with stitching vias
  • DRV8833 exposed pads require thermal vias to GND plane

  • Purpose

  • Power Tree

  • Key Components from Uploaded BOM

  • Driver Mapping

  • ESP32-S3 GPIO Mapping

  • Matrix Netlist Rule

  • Layout Targets from Uploaded Workflow