Flipdot Matrix PCB Design Review
Architecture change: switch from ESP32-S3 SuperMini dev board to ESP32-S3-MINI-1 module surface-mounted directly on the PCB.
This solves the GPIO shortage (the bare module exposes 33+ usable GPIO vs the SuperMini's ~12), eliminates dev-board header alignment issues, and produces a cleaner single-PCB design. JLCPCB stocks this module and will place it via PCBA.
Please remove the ESP32-S3 SuperMini header from the schematic and replace it with the following:
- Main module ESP32-S3-MINI-1-N8 — Espressif ESP32-S3 module with 8MB flash, no PSRAM
LCSC part number: C2913201
Package: castellated LGA, 15.4mm × 20.5mm × 2.4mm, 65 pins
Built-in PCB antenna, crystal, and flash — no external support needed for those
Critical pin connections:
All VDD3P3 pins (multiple — pins 1, 3, 4, 17, in the module's "P" pins): tie to VCC_3V3 net
All GND pins: tie to GND net
EN (pin 45): reset input. Pull to VCC_3V3 via 10kΩ, then to reset button → GND
IO0 (pin 27): boot strapping pin. Pull to VCC_3V3 via 10kΩ, then to boot button → GND
IO19 (pin 23): USB D-
IO20 (pin 24): USB D+
IO45 (pin 7): strapping pin, leave at hardware default (pull to GND via 10kΩ for normal flash voltage)
IO46 (pin 26): strapping pin, leave at hardware default (no pull, or pull to GND)
All other GPIO pins (IO1, IO2, IO4-8, IO15-18, IO21, IO33-41, IO47, IO48) route to the DRV8833 driver inputs per the original spec — the GPIO assignment table from the project brief stays unchanged.
2. USB-C interface (programming + power)
Wire the existing USB-C connector (J1) as follows:
VBUS pins → existing SS14 Schottky → VM_5V net (already in place)
CC1, CC2 pins → 5.1kΩ pulldowns each (already in place)
D+ pin → through USB ESD protection (see component 3) → ESP32-S3 IO20
D- pin → through USB ESD protection → ESP32-S3 IO19
Shield/GND → GND
- USB ESD protection USBLC6-2SC6 — 6-pin USB ESD protection array
LCSC part number: C7136
Package: SOT-23-6
Connections:
Pin 1 (I/O1) → USB D-
Pin 6 (I/O2) → USB D+
Pin 3 (Vbus) → VM_5V
Pin 2, 4, 5 (GND) → GND
After this chip, D- continues to ESP32 IO19 and D+ to ESP32 IO20
- Auto-reset circuit (standard ESP32 bootloader entry) This circuit lets esptool toggle reset and boot pins via USB DTR/RTS signals, so you don't need to press buttons to flash firmware. It's the standard ESP32-S3-DevKitC-1 reference design. Components:
Q1, Q2: 2× MMBT2222ALT1G NPN transistor, SOT-23 (LCSC C8589)
R5, R6, R7, R8: 4× 10kΩ 0805 resistors (already in BOM family — LCSC C17414)
Note: this circuit assumes USB-CDC for serial communication (built into ESP32-S3 via native USB). The DTR and RTS lines come from the USB CDC interface internally, not from a separate USB-UART chip. So actually — let me correct this. With ESP32-S3 native USB, you don't need the auto-reset transistor circuit at all. The ESP32-S3 handles reset/boot entry via USB commands internally.
Skip the auto-reset transistor circuit. ESP32-S3 native USB handles this automatically.
You only need:
Manual reset button (SW1, existing): one side to EN, other side to GND
Manual boot button (SW2, new): one side to IO0, other side to GND. Add as a second tactile switch.
- Strapping pin pullups Required for the ESP32-S3 to boot correctly:
R9: 10kΩ from EN to VCC_3V3 (so EN is high by default; pressing SW1 pulls low for reset)
R10: 10kΩ from IO0 to VCC_3V3 (so IO0 is high by default for normal boot; pressing SW2 pulls low for download mode)
R11: 10kΩ from IO45 to GND (selects 3.3V flash voltage — must match the module variant)
R12: 10kΩ from IO46 to GND (selects normal boot mode at startup)
All four are 0805 resistors, LCSC C17414.
6. Decoupling for the ESP32-S3-MINI-1
The module has multiple VDD pins that need close decoupling:
1× 10µF 0805 ceramic (LCSC C15850) placed within 2mm of any VDD pin — bulk decoupling
3× 100nF 0805 ceramic (LCSC C49678) one per VDD pin group, placed within 1mm of each VDD pin
Reference the Espressif ESP32-S3-MINI-1 datasheet, section "Schematics," for the canonical decoupling pattern
These are in addition to the existing decoupling on VM_5V and VCC_3V3 rails.
7. Antenna keepout zone
This is a PCB layout rule, not a schematic addition, but include it as a design note:
The ESP32-S3-MINI-1 has a built-in PCB antenna at one edge of the module. On the PCB layout:
Mark an 11mm × 6mm clearance zone extending outward from the antenna edge of the module
This zone must contain: no copper traces, no copper pours, no ground plane, no components
Both top and bottom layers must be clear in this zone
The module should be placed so this clearance extends off the edge of the board if possible — this is the cleanest layout
Refer to the ESP32-S3 Hardware Design Guidelines, section "General Principles of PCB Layout for Modules," for the exact keepout dimensions.
8. Power requirements
The ESP32-S3-MINI-1 module only accepts 3.3V on its VDD pins — never 5V. The existing AP2112K-3.3 LDO supplies this. Confirm the schematic doesn't accidentally route VM_5V to any module pin.
Module current draw:
Active (Wi-Fi TX peak): up to 500mA momentary
Active (no radio): ~80mA typical
Light sleep: ~240µA
The AP2112K-3.3 is rated for 600mA output, which is sufficient with margin. Make sure the LDO's output capacitor is at least 10µF (already in BOM).
9. Updated BOM additions
DesignatorPartLCSCQuantityU10ESP32-S3-MINI-1-N8C29132011U11USBLC6-2SC6 ESD protectionC71361SW2Tactile switch (boot button)C3188841R9-R1210kΩ 0805 resistorC174144Additional 100nF caps near U10 VDD pins100nF 0805C496783
10. Updated BOM removals
DesignatorRemovedH1, H22× 1×9 female header (was for SuperMini)
Net BOM change: ~$2-3 cheaper than the SuperMini + 2× MCP23017 fix, and significantly more capable.
Confirm before proceeding
Please confirm:
ESP32-S3-MINI-1-N8 (C2913201) is in JLCPCB's PCBA library
The 11mm × 6mm antenna keepout zone can be accommodated in the current PCB layout (preferably extending off one edge of the board)
ERC passes cleanly with the new module footprint and all pins properly connected or marked NC
Once confirmed, proceed with the rest of the schematic exactly as originally specified — GPIO assignments, driver chips, matrix, and power all stay unchanged.
Thought for 14 sec
Confirmed — I’ll replace the SuperMini-header approach with the ESP32-S3-MINI-1 module, add USB ESD, boot/reset strapping, module decoupling, update the notes/firmware, then re-run ERC and fix remaining issues.
Worked for 10 mins 50 sec
Implemented the ESP32-S3-MINI-1 architecture change: added U10, USB ESD, boot/reset strapping, module decoupling, native USB wiring, and replaced the power-only USB-C with a USB2-capable connector. ERC is clean with zero warnings/errors, and U10 is powered only from VCC_3V3, not VM_5V.
Notes/caveats are captured in ESP32-S3-MINI-1 Architecture Change, and I updated Firmware Getting Started for the direct-module pinout.
The board has enough area for the 11 mm × 6 mm antenna keepout, but exact keepout validation happens during placement. Ready to proceed to PCB placement when you approve.
Place module at edge
Run post-placement DRC
Review BOM impact
Check antenna keepout
Refine this doc
Ask about this doc
Flipdot 6x8 Matrix Controller — Design Review Notes
Baseline Architecture
- 48-cell magnetic flip-dot matrix: 6 columns x 8 rows.
- Each cell is a non-polarized ~10uH shielded SMD inductor under a mechanically latched magnet.
- Drive method: bipolar row/column matrix using tri-state half-bridge outputs.
- Select one cell by driving one row rail and one column rail in opposite states; all non-selected rows/columns remain high-Z.
- Main rails: USB-C VBUS -> SS14 -> VM_5V; VM_5V -> AP2112K-3.3 -> VCC_3V3.
- Drivers: 7x DRV8833, using only OUT1 of each bridge as a tri-state half-bridge output.
- MCU: ESP32-S3 SuperMini on 2x 1x8 female headers; board power feeds module 5V pin, module 3V3 pin left unconnected.
Hard Requirements
- Matrix pitch: 6.0mm horizontal x 5.0mm vertical, non-negotiable.
- Board target: 70mm x 60mm, 2-layer JLCPCB economy, top-side assembly only.
- Inductor target: Bourns SRR4528A-100M / LCSC C7449 or drop-in equivalent, 10uH, >=1A saturation.
- DRV8833 target: TI DRV8833RTYR / LCSC C154936, WQFN-16 exposed pad.
- LDO target: AP2112K-3.3 / LCSC C460340.
- USB-C CC1 and CC2 each require independent 5.1k pulldown to GND.
- Every DRV8833 requires local 100nF + 10uF VM decoupling and exposed pad to GND with thermal vias.
- AOUT2 and BOUT2 are intentionally no-connect for this matrix half-bridge topology.
Schematic Review Checklist
- Both DRV8833 VM pins tied to VM_5V on every driver.
- DRV8833 GND pin and exposed pad tied to GND.
- AISEN/BISEN tied to GND when current sensing is unused.
- nSLEEP pulled to VCC_3V3 on every driver, either per-chip or via shared pull-up if acceptable by datasheet leakage.
- nFAULT may be tied together and pulled up to VCC_3V3, optionally routed to a spare GPIO.
- VINT left floating if datasheet confirms no external connection required.
- Matrix nets named ROW0..ROW7 and COL0..COL5 consistently.
- Each inductor connects to exactly one ROW net and one COL net.
- ESP32-S3 GPIO 19/20 avoided for module USB, GPIO 26-32 avoided for internal flash, GPIO0 avoided unless boot handling is added.
Layout Review Checklist
- 48 inductors placed in exact 6 x 8 grid, 6.0mm x 5.0mm pitch; cumulative error =30 mil, not daisy-chained through driver pins.
- ROW/COL rails >=20 mil.
- Logic GPIO traces 6-8 mil acceptable.
- Bottom layer mostly GND fill with stitching vias near perimeter and driver pads.
- DRV8833 decoupling caps within 3mm of VM pins where possible.
- DRV8833 exposed pads have 4-5 thermal vias to bottom GND fill.
Review Concerns to Verify During Design
- Half-select sneak paths: selected row/column pair should be the only closed current path; non-selected cells have one terminal high-Z.
- Bulk capacitance: 1000uF supports only about 0.5C/V * 1V? Practical charge at 0.5V droop is 0.5mC, not 5mC; USB source and series resistance dominate repeated pulses. Consider 2200uF if animation pulse density is high.
- Rail ringing: 30-35mm, 1A inductive pulse rails may ring; prefer tight return path, GND fill, local decoupling, and optionally firmware slew/pulse shaping before adding ferrite beads.
- DRV8833 pulse mode: verify input truth table, current limit/sense behavior, nSLEEP, nFAULT, VINT, and OUTx behavior from datasheet before wiring.
- Magnetic coupling: shielded inductors and high-Z non-selected coils should reduce electrical coupling; mechanical flip threshold must be validated empirically.
- Thermal: 2-layer is likely acceptable for short pulses, but exposed-pad vias and copper area are mandatory; 4-layer improves thermal spreading and return paths if cost allows.
Deferred v2 Items
- LiPo battery and charger.
- BLE/WiFi remote control UX.
- Larger matrix variants.
- Alternate magnet/coil geometry.
Baseline Architecture
Hard Requirements
Schematic Review Checklist
Layout Review Checklist
Review Concerns to Verify During Design
Deferred v2 Items
