Production target is now nRF54LM20A-PAAA / CSP98. The existing QGAA design is frozen as provisional/reference-only and must not be routed or adapted into the PAAA implementation. No schematic replacement was performed because a usable exact A-variant PAAA part and an ingestible official PAAA reference-layout package are not currently available in Flux.

The proposed PAAA interface uses host SPIS00 on P2 and PAW SPIM23 on P3. This is datasheet-supported at the pin-planning level, but simultaneous transparent interception and radio coexistence remain conditional and unvalidated. Production remains NO-GO / DO NOT RELEASE.

Priority for this review:

No nRF52840 or nRF54L15 electrical values are used.

The following table is the frozen QGAA reference only and is not valid for PAAA balls or routing.

HOST_MOTION is connected to TP21 and PAW_MOTION to TP22. The signal map has no GPIO reuse and preserves all required interface/test access.

Conflict check: no GPIO is reused; each SPI interface remains on one port; P2.01 and P3.03 are clock-capable. P3 is available only on CSP98 and supports the required 8 MHz maximum GPIO rate. The map avoids copying QGAA ball numbers and moves PAW SPI/control and buttons to independently verified PAAA balls.

Authoritative evidence located:

Availability failures:

Therefore the official CSP98 land pattern, paste/mask data, escape routing, production stackup, and full reference topology cannot be verified inside Flux. The safe stop rule applies: do not remove QGAA U1, create a guessed footprint, or partially add PAAA support circuitry.

SPIS and normal SPIM instances are documented to support up to 8 Mbps, so the selected SPIS00/SPIM23 pair has sufficient headline rate capability. Transparent behavior remains unproven because maximum rate is not equivalent to deterministic pass-through latency.

SPIM23 has a 16 MHz core and an even prescaler divisor from 2 through 126. Exact 2.5 MHz generation would require divisor 6.4, which is not representable. Firmware must capture the stock rate more tightly and validate an available divider/rate against the PAW and stock-host timing before claiming transparent reproduction. This does not presently require a hardware change.

Anomaly 8 causes wrong MOSI data when:

CPHA remains unresolved, and the approximately 2.5 MHz SPIM23 target requires a prescaler greater than 2. Therefore anomaly 8 is conditionally applicable and must remain in the firmware requirements until mode/timing capture proves otherwise.

Documented workaround for PRESCALER > 2:

Anomaly 54 is stated for SPIS generally and therefore applies to the selected SPIS00 unless Nordic documents an exception. SPIS00 SDO must not float while the peripheral is idle/deselected. The errata permits an internal or external pull-down.

No additional SPIS00-specific anomaly was identified in the reviewed Rev-1 errata. SPIS00 shares its peripheral ID/resources with other 00 functions, so SPIM00/SPIS00/UARTE00 cannot be enabled simultaneously with each other; the selected PAW SPIM23 has a different instance ID and does not create that shared-ID conflict.

No reviewed authoritative Nordic source supports a blanket “No SPI00 while radio is on” prohibition. SPIS00 is in the MCU domain and RADIO is in the radio domain. The reviewed radio anomalies require documented constant-latency/power-mode handling under their stated conditions, but do not prohibit SPIS00 operation.

The blanket constraint is removed. Coexistence remains a firmware/bench validation item: verify transparent SPI latency, DMA/interrupt scheduling, current consumption, and radio operation under concurrent load before treating it as proven.

The layout currently contains physical placeholders and must not be described as having no footprint or stackup:

Both are provisional / non-production / DO NOT RELEASE. Neither is an approved LM20A-QGAA production definition. Final QFN52 land pattern, exposed-pad/paste/via implementation, RF constraints, impedance geometry, and production stackup remain blocked pending official evidence.

These QGAA physical placeholders are now frozen reference-only. They must be removed during the eventual atomic PAAA replacement and must not be scaled, remapped, or otherwise adapted to CSP98.

QGAA-specific power, clock, RF, and footprint details are frozen and must not be adapted. PAAA datasheet/reference-circuit BOM values were located, but the following PAAA implementation details remain blocked from mutation until the official archive is readable and the exact part is usable:

Firmware-controlled PAW power switching, five manual bypass paths, SWD/test access, buttons, reset interception, and both MOTION nets must be preserved. The eventual PAAA rebuild must also add the required removable 0 Ω DeltaTap VDD link and reconcile POWER_ISO_EN to PAW_VDD_EN.

The four QGAA ERC power errors remain because no unsafe partial replacement was performed. They are not yet resolved; they are expected to be superseded only after the complete official PAAA power/reference section is installed and validated.

NO-GO / DO NOT RELEASE. Do not route around QGAA and do not partially replace U1. Resume electrical mutation only when the exact nRF54LM20A-PAAA part plus readable official v0.6 reference libraries/production files are available, allowing an atomic replace–rewire–support-circuit rebuild and ERC review.

PAW3395 datasheet for the exact family Especially supply limits, SPI electrical requirements, RESET/MOTION behavior, startup timing, and decoupling. This helps validate the PAW-side load switch and GPIO behavior instead of relying only on donor measurements. Exact PAW load-switch datasheet once Flux picks the part RDS(on) operating voltage around 2 V enable threshold rise time / soft-start reverse-current behavior leakage when off This is important for proving the PAW actually powers fully down and isn’t back-fed. Exact crystal datasheets/MPNs from Nordic’s PAAA BOM 32 MHz crystal 32.768 kHz crystal if you decide to populate one Gives Flux the real load capacitance, ESR, tolerance, and footprint rather than just copying nominal capacitor values. JLCPCB manufacturing capability/rules Especially for: 0.35 mm CSP pitch minimum via/drill solder-mask registration via-in-pad capability/cost minimum trace/space supported layer stackups CSP assembly rules This matters a lot now that you’re using CSP98. Your mechanical constraint drawing A simple annotated image/PDF would help more than another text document: 22 × 25 mm target boundary hard 25 mm dimension antenna edge JST-PH location/orientation PAW-facing edge bypass rows SWD/pogo area M4/M5 daughterboard keepout battery/wheel keepouts A dedicated connector/bypass geometry sheet Lock: JST-PH 6-pin, 2.0 mm pitch VDD/GND/M1/M2/M4/M5 order two 5-position bypass rows 1.27 mm pitch along rows ~1.8 mm row-to-row center spacing drill/pad dimensions signal order Current firmware interface contract Give it the newest version only, with: SPIS00 SPIM23 ~2.5 MHz measured stock clock 8 MHz design headroom high-Z startup PAW_VDD_EN both MOTION nets manual bypass with no BYPASS_n

The biggest addition I’d pursue before serious routing is actually JLC’s CSP manufacturing constraints. Nordic tells Flux how the chip should be laid out; JLC tells it whether that layout can actually be manufactured economically.

The five manual bypass paths must be implemented as two aligned parallel rows of plated wire/solder pads, not as unrelated jumper footprints elsewhere on the PCB. One row is HOST/stock-MCU-side wire termination and the other is PAW/sensor-side wire termination. Use 5 positions at 1.27 mm pitch within each row, approximately 1.8 mm row-to-row center spacing, with matching SCLK/MOSI/MISO/NCS/RESET positions directly opposite each other. Target approximately 0.8 mm drilled holes unless manufacturing review requires adjustment. Normally the rows remain electrically separate and route to the two sides of DeltaTap. Manual bypass is performed by solder-bridging each matching HOST↔PAW pad pair.

Right now Flux clearly understands the electrical concept—five manual bypass paths for SCLK/MOSI/MISO/NCS/RESET—but the files do not clearly define the physical hole geometry or that those holes are also intended as the wire termination points for the two cut sides of the mouse bus.

What you actually want is:

Two parallel rows of 5 plated through-holes/pads 1.27 mm pitch along each row About 1.8 mm center-to-center between rows Around 0.8 mm drill as the current target Matching signals directly opposite each other: SCLK MOSI MISO NCS RESET

Each row has a different purpose:

HOST/MCU row

Wires from the original mouse-MCU-side traces terminate here. Those nets then route into DeltaTap's SPIS00 side.

PAW row

Wires from the lifted PAW3395 pins terminate here. Those nets then route into DeltaTap's SPIM23 / PAW-control side.

Normally, the two rows are electrically separated and DeltaTap sits between them.

The things Flux should know before it starts placement are:

MCU: nRF54LM20A-PAAA / CSP98. Authority: Nordic PAAA Reference Layout v0.6. Board target: 22 × 25 mm. Absolute max: ~25 × 25 mm. 25 mm length is hard. Installed height: ≤ ~6 mm total. Board thickness: not frozen; follow Nordic/reference/manufacturing needs, but total assembly still has to fit the 6 mm envelope. Physical interfaces

6-pin JST-PH, 2.0 mm pitch

2.0 V GND M1 M2 M4 M5

Tell Flux the exact connector orientation you want before placement:

cable exits toward which edge? top-entry or side-entry? should it sit flush at the board edge?

That is still one mechanical detail I don’t think we’ve frozen.

SPI / RESET bypass area

Five signals: SCLK MOSI MISO NCS RESET Two parallel rows: MCU/HOST side PAW side 1.27 mm pitch within each row. Roughly 1.8 mm center-to-center between rows. Corresponding signals directly opposite each other. Around 0.8 mm drill if you want through-holes/wire access. Normally open; user manually bridges matching pairs. No automatic bypass circuitry. No BYPASS_n.

I’d also explicitly tell it that the bypass area needs to be easy to reach with an iron after assembly, not buried under the MCU or RF section.

PAW wiring

Flux needs a compact wire-pad area for:

HOST SCLK/MOSI/MISO/NCS/RESET PAW SCLK/MOSI/MISO/NCS/RESET HOST_MOTION PAW_MOTION PAW VDD / GND as required

Those wire interfaces should stay near the PAW-facing edge of the board so you aren’t running enamel wires across the PCB.

RF floorplan

This is important to tell it before placement:

RF antenna at the outermost board edge. Follow Nordic PAAA reference geometry/keepout as closely as practical. No JST, bypass pads, pogo pads, SPI wiring, large copper, or tall components in the antenna keepout. Keep the RF feed short. Prefer antenna edge facing away from the PAW/mouse PCB/battery as much as the mechanical envelope allows. Do not shrink or improvise the Nordic RF keepout just to make everything fit. Debug

Keep accessible:

SWDIO SWCLK nRESET 2.0 V GND status LED one spare test GPIO optional UART pads

Pogo/debug pads should be somewhere you can actually reach after the board is mounted and should not require pressing force through the PAW sensor.

Power DeltaTap powered from mouse ~1.98–2.0 V. Removable 0 Ω VDD link. Firmware-controlled PAW load switch required. PAW_VDD_EN required. No 3.3 V mouse-side signals. Avoid excessive bulk capacitance because of startup inrush. Follow Nordic PAAA power/DEC implementation rather than the old provisional QGAA circuit. Digital architecture Host = SPIS00 PAW = SPIM23 Stock SPI currently ~2.5 MHz Hardware should comfortably support ≥8 MHz Separate HOST and PAW SPI nets. Separate HOST_MOTION and PAW_MOTION. M1/M2/M4/M5 included in V1. All mouse-facing outputs boot high-Z. PAW RESET is low-only/open-drain. What I’d make Flux accomplish tomorrow

In this order:

Import/create the verified PAAA CSP98 component from Nordic’s files. Replace the QGAA MCU section completely. Apply Nordic PAAA power/clock/RF reference circuitry. Finalize the PAAA pin map for SPIS00/SPIM23 + everything else. Reconcile the schematic against all current requirements. Run ERC and report every remaining issue. Freeze schematic. Produce a placement proposal inside 22 × 25 mm showing: antenna MCU JST bypass rows PAW wire pads SWD/pogo pads power switch Do not spend a ton of quota routing yet until you approve that placement. Export/save the entire editable project before your weekly quota runs out.

The biggest information you're still missing for Flux is probably the exact JST orientation and the preferred edge/location for the PAW/bypass wiring area. Once those two are decided, Flux has enough to make a meaningful physical placement instead of guessing.6