Diseño de PCB Regulador de Voltaje

flux

0:00

Work completed
  • Project description and system architecture distilled and mermaid diagram added (steps 1.1, 1.2).
  • All key components added: transformer (T1), bridge diodes (D1–D4), 2200 µF bulk caps (C3–C6), 100 nF decoupling caps (C7–C10), LM317KCS (U2/U4), LM337T (U3), digital LED voltmeters (U5/U6), 220 Ω resistors, 5 kΩ potentiometers (R11/R12), reverse-polarity diodes (D13/D14), connectors (J1–J3), mounting holes.
  • Nets fully connected per schematic plan (step 4.2).
  • Generic passives assigned appropriate SMD/through-hole footprints (step 6.1).
Tasks not yet done
  • Board outline: calculate bounding box and set PCB size (6.4).
  • Ground fill and via stitching for plane (6.5).
  • Mounting solution and mounting holes placement (6.6–6.7).
  • Stackup and layer assignments (6.2–6.3).
  • Net classification and trace-width rules (7.1–7.2).
  • Component placement, grouping, and separation (8.1).
  • Auto-routing of nets (9.1).
  • ERC/DRC review, thermal/mechanical checks (10.x).
  • BOM enrichment and manufacturability review (11.x).
Tasks marked “can’t do”
  • Messaging user with the architecture diagram (1.3).
  • Automated ERC reviews and rating checks (5.1–5.3).
  • Setting stackup and layer roles (6.2–6.3).
Success criteria
  • PCB integrates all specified components: incomplete (layout not yet placed/routed).
  • Isolation zones and clearances per AC/thermal rules: incomplete.
  • Stable ±0–24 V regulation with heatsinks: untested (layout pending).
  • DRC error-free and mechanical anchors: pending.
Next recommended step Prepare the PCB outline and board shape: use the layout tool to fetch transformer footprint extents and heatsink keep-out areas, then set the board dimensions with at least 10 mm isolation margins.
101 days
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    Una fuente de voltaje regulables de positivo a negativo y tierra de 50 volts thumbnail
    Adjustable ±0–24 V Dual-Rail Linear Power Supply Module with LM317/LM337 Regulators and Integrated 36 VAC Center-Tapped Transformer Interface

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