• Prototype/validation build for modular “Technomancy” tiles.
• Tiles snap together magnetically in a tabletop physical array.
• The Earth tile powers the array and broadcasts discovery/pulse messages to connected tiles.
• Intended for low-voltage battery-powered interactive objects, not for safety-critical or outdoor use in this revision.

• Provide regulated power to neighboring tiles through edge pogo contacts.
• Detect and communicate with attached tiles over robust edge-to-edge differential links.
• Broadcast a repeating source/pulse message from the Earth tile.
• Support firmware development and debug access.
• Fit inside the specified hollow 100 mm flat-to-flat hex shell.

• Single-cell LiPo battery input.
• USB-C charging input recommended for prototype convenience.
• 5 V edge power rail for downstream tiles.
• 3.3 V logic rail for MCU and communication ICs.
• Six identical edge electrical ports.
• Mechanical magnet pockets, pogo-pin holes, keyed male/female collar geometry, M2 screw pillars, and Uruz rune engraving.

Diagram

• Single-cell LiPo battery powers the tile.
• USB-C 5 V input charges the LiPo through a power-path/load-sharing charger, not a basic charger tied directly to the system load.
• A boost regulator creates the 5 V edge power bus.
• A 3.3 V regulator powers the MCU, UART bridges, and RS-485 transceivers.
• Edge 5 V output should be split into per-edge protected branches with current limiting and reverse-current blocking before physical prototype release.

• ESP32-S3-class module preferred for rapid prototyping, native USB, many GPIOs, Arduino/ESP-IDF support, and optional Wi-Fi/BLE.
• Firmware drives packet routing, topology discovery, edge-port state, and pulse broadcasting.

• Selected architecture: independent point-to-point half-duplex RS-485 differential link on each edge.
• Rationale: a shared passive CAN bus is electrically awkward in arbitrary hex meshes because the topology becomes branches/loops/stubs with no stable pair of termination endpoints. Per-edge differential links keep each physical connection simple and let firmware route packets across the tile graph.
• Edge pinout becomes: 5V, GND, RS485_A, RS485_B.
• Each edge gets its own RS-485 transceiver and local termination option.
• The MCU reaches six edge UARTs through external multi-UART bridge ICs over SPI.
• Firmware must use framing, CRC, deduplication, and hop-count/TTL to prevent routing loops.

• Six edge connectors, each with four pogo contacts:
  1. 5V_EDGE_n
  2. GND
  3. RS485_A_n
  4. RS485_B_n
• Magnets are mechanical alignment only and must not carry current.
• Edge 1: male shear collar, North magnet pocket.
• Edge 2: female recessed pocket, South magnet pocket.
• Edges 3–6 require a final alternating/keying scheme before mechanical CAD/layout.

• Exposed pogo contacts should receive ESD protection for RS485_A/RS485_B and edge power.
• Each 5 V edge branch should include current-limited switching and reverse-current protection to prevent one damaged/misaligned edge from collapsing the whole mesh.
• Multiple Earth/source tiles must not directly parallel boost outputs without ideal-diode/load-switch policy.

• Battery: single-cell LiPo, capacity TBD.
• Edge rail: 5 V output for neighboring tiles.
• Logic rail: 3.3 V.
• Runtime target: TBD after battery capacity and downstream tile loads are defined.
• Sleep current is not optimized in the first proof-of-concept unless requested.

• Prototype-first design.
• SMD default for compact fit inside the tile.
• Use real library parts where available; generic passives are acceptable for resistors/capacitors/inductors.
• Provide test points for BAT, 5V_EDGE, each per-edge 5 V branch, 3V3, GND, RS485_A/B, EN/BOOT, and charge status.

• SPI from MCU to UART bridge ICs.
• Six half-duplex UART/RS-485 links with DE/RE direction control.
• Boot/reset access.
• Battery voltage measurement recommended through resistor divider into ADC.
• Optional charge-status and edge-fault GPIOs.
• Pulse/discovery protocol uses a framed packet protocol over per-edge half-duplex links.
• Assign a unique tile ID in firmware or via future hardware ID option.

• Regular hexagon, flat-to-flat width: 100 mm.
• Height: 12 mm.
• Uniform outer wall thickness: 2.5 mm, forming a hollow internal electronics bay.
• Top face: engraved Uruz rune geometry, 1.5 mm line width, 1.2 mm inlay depth.
• Bottom shell floor: four recessed structural screw pillars for self-tapping M2x6 mm screws.
• Edge 1: 30 mm wide x 1.5 mm deep solid rectangular shear collar centered on height profile; 3.2 mm diameter x 2.0 mm deep North magnet pocket at midpoint; four 2.5 mm pogo holes flanking magnet left/right by 8 mm.
• Edge 2: 30.4 mm wide x 1.7 mm deep female pocket; matching 3.2 mm South magnet pocket and four 2.5 mm pogo holes.
• Exact interpretation of “four holes flanking left/right by exactly 8 mm” must be clarified in CAD: likely a 4-contact row centered around the edge midpoint with magnet in the center.

• Magnets are not electrical conductors; they are alignment/keying only.
• Robust bus choice: per-edge point-to-point RS-485, replacing single-ended Data IN/Data OUT naming with RS485_A/RS485_B.
• The six edge data ports are electrically independent and are routed in firmware; they are not tied into one passive bus.
• Use local termination options on each point-to-point edge link rather than global bus termination.
• Exposed 5 V contacts should be individually protected/current-limited per edge before final layout.
• Start with a prototype-current assumption of 5 V / 1 A total edge output until tile load measurements exist.

• The Earth tile should be rechargeable over USB-C.
• The MCU may be an ESP32-S3 module unless the user prefers Arduino Nano Every or another MCU.
• Wireless is optional and not required for rev A functionality, but an ESP32 module introduces RF layout/regulatory considerations.
• All six edges should ultimately support electrical mating, but only edge 1 and edge 2 mechanical details are currently specified.
• The initial schematic may use standard board connectors to represent edge pogo interfaces until exact pogo connector MPNs are selected.

• Confirm final edge 3–6 mechanical/keying pattern.
• Select exact LiPo cell capacity, connector type, and charge current.
• Select exact boost current limit based on maximum number of downstream tiles.
• Finalize per-edge high-side switch / eFuse part and current limit.
• Choose exact pogo-pin connector MPN/footprint.
• Decide whether firmware programming is via native USB, USB-UART, or external serial header.

• Initial specification created from the two pasted user notes.
• Bus architecture updated after review from shared CAN to per-edge point-to-point RS-485 for arbitrary mesh robustness.
• Earth tile schematic direction defined: LiPo + USB-C power-path charging + 5 V boost + 3.3 V logic + ESP32-S3 module + dual quad-UART bridges + six RS-485 edge links.