Project Start
Worked for 23 mins 30 sec
The rebuild attempt still cannot escape the three small QFN pads and introduced 37 copper conflicts, so I’m rolling back the entire U2 rebuild rather than leaving an unsafe partial power stage.
Worked for 3 mins 16 sec
The coordinated U2 rebuild still failed: the router could not escape the BOOT, VCC and PGOOD pads, and the attempted rebuild produced 37 copper conflicts. I rolled back the rebuild and removed its conflicting copper.
The U2 block requires either:
- Manual editor routing with direct visual control, or
- A corrected U2 footprint/keepout definition; the current QFN pad geometry appears incompatible with the routing engine.
USB and unrelated interface routing were not changed.
remove all routing
Worked for 47 sec
Removed all persisted PCB routing traces and vias. The schematic, component placement, stackup, and routing constraints remain unchanged.
Confirm clean baseline
Check placement again
Document routing reset
Plan U2 fix
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Project Specification
Project Overview
Status: Review — schematic-stage design complete; awaiting ERC disposition and physical-interface verification. Production-intent universal replacement for the common JBD BMS UART Bluetooth module, adding Wi-Fi/BLE and environmental sensing.
Intended Use
Mounted inside a plastic 12 V or 24 V leisure-battery enclosure and connected to the shared four-wire JBD accessory UART harness. Intended for 1,000-unit manufacture after harness, probe, RF, EMC, and environmental validation.
What the Device Should Do
- Power from the JBD pack-accessory connection over 5–36 V continuous.
- Exchange nominal 3.3 V UART data with common JBD BMS models.
- Provide Wi-Fi/BLE hardware for cloud/API, MQTT, and Home Assistant firmware.
- Measure two permanently wired external battery temperatures and internal RH/temperature.
- Support local USB-C development/service and unattended recovery from firmware lockup.
Main Features
- Certified ESP32-C3 module with integrated PCB antenna.
- Native USB device/programming where supported; USB-C bench power with no backfeed.
- BOOT/RESET controls and production programming/test access.
- Independent ultra-low-power external watchdog/supervisor.
- Two switched 10 kΩ-at-25°C NTC channels (provisional B25/85=3950 K) with 22 kΩ, 1% top resistors, filtering, and external-lead protection; required measurable range −40°C to +125°C.
- Industrial-temperature I2C humidity/temperature sensor.
- Firmware-disableable status indication only.
System Architecture
Text
JBD 4-wire harness -> reverse/transient/ESD protection -> wide-input low-Iq 3.3 V buck -> ESP32-C3 USB-C -> CC/ESD/current protection -> isolated 3.3 V service power ----------------------^ JBD UART -> series + 3.3 V clamp/ESD -> ESP32-C3 UART ESP32-C3 -> switched NTC excitation -> NTC1/NTC2 ADC inputs ESP32-C3 <-> I2C RH/T sensor External watchdog -> ESP32 enable/reset; service GPIO <- ESP32
Hardware Subsystems
- JBD connector and pack protection.
- 3.3 V low-Iq wide-input buck supply sized for Wi-Fi peaks.
- USB-C device/service power and native USB data.
- ESP32-C3 compute/radio, strapping, boot/reset and production test.
- Protected JBD UART.
- Dual external NTC analog front ends.
- Internal I2C humidity/temperature sensing.
- Independent watchdog/supervisor and optional low-power status LED.
Interfaces and Connections
- JBD connector: CAX HY2.0-4P-WT (LCSC C722729), 2.0 mm pitch, 4-position locking right-angle SMT header, library footprint
CONN-SMD_HY2.0-4P. Enforced board numbering from the mating view is pin 1 GND, pin 2 module RX / JBD-BMS TX (JBD_BMS_TX_RAW), pin 3 module TX / JBD-BMS RX (JBD_BMS_RX_RAW), pin 4 VDD/full-pack (PACK_RAW). Mechanical solder tabs 5 and 6 are non-electrical. The side-entry mating opening faces outward at the left PCB edge. This is explicitly not a JST XH footprint. - USB-C USB 2.0 device: independent 5.1 kΩ CC1/CC2 Rd; native D+/D− dedicated.
- NTC1 and NTC2: separate two-wire interfaces for 200 mm M8 ring-lug probes. Production probe procurement requirement: 10 kΩ at 25°C, B25/85 nominal 3950 K (or supplier curve/table), R25 tolerance ≤±1%, beta tolerance ≤±1%, specified conversion accuracy through +125°C, continuous operating range including −40…+125°C, sealed ring-lug encapsulation rated ≥125°C, high-temperature cable insulation (ETFE/PFA/PTFE or equivalently certified), and strain relief rated ≥125°C. No production probe MPN is approved until supplier documentation confirms all items.
- Production access: 3V3, GND, EN/RESET, BOOT, UART TX/RX, native USB D+/D− as practical test pads/header.
Power and Runtime Expectations
Low-power hardware must permit firmware-selected sleep/reporting intervals. Pack input is 5–36 V continuous; all upstream parts require margin above 36 V. USB-C supplies bench-service power but must not backfeed PACK+ or the BMS harness.
Power Tree and Power Budget
Final values and datasheet evidence are maintained in Design Notes and Power Budget. Final nominal 3V3 peak is ~348 mA (or ~448 mA with the SHT41 heater at maximum); the selected 600 mA LMR36506 has margin. Core typical sleep is ~9.1 µA before protection leakage, with a production target below 30 µA at 25 °C.
Manufacturing and Assembly Expectations
- SMD, production-oriented footprints; target electronics BOM £5–£10 at 1,000 units excluding enclosure and temperature-probe cables.
- All critical active parts rated at least −40…85°C.
- Availability and lifecycle reviewed before manufacture.
- No PCB layout in this phase.
Firmware-Relevant Hardware Requirements
- PlatformIO/Arduino starter based on final GPIO mapping.
- Native USB programming/serial, BOOT and RESET.
- Internal watchdogs plus external watchdog servicing.
- OTA dual-partition rollback, repeated-failed-boot recovery, and factory/service USB path.
- NTC excitation controlled only during sampling; LED fully disableable.
Physical Design Expectations
PCB size unconstrained. Later layout must place the ESP32-C3 module antenna at a board edge with the certified-module keepout free of copper/components and account for the plastic enclosure.
Important Design Decisions
- Wide-input buck, never a pack-fed LDO.
- ESP32-C3 certified module with integrated antenna unless verified alternative is superior.
- Passive UART series/clamp/ESD protection; no active level shifter unless JBD electrical verification requires it.
- Probe electrical basis: 10 kΩ NTC at 25°C, provisional B25/85=3950 K ±1%, R25 ±1%, two wires, 200 mm, M8 ring lug. +125°C is a required measurement point, not a storage-only rating.
Assumptions
- Shared JBD UART is nominal 3.3 V logic.
- J1 uses the closest exact-family library entry, CAX HY2.0-4P-WT. The library entry and LCSC listing verify HY2.0 naming, 4 positions, 2.0 mm pitch, SMT, and right-angle orientation, but no manufacturer mechanical drawing/datasheet is attached. Therefore locking-ramp geometry, housing interchangeability, and the mating-view pin-1 convention remain an unavoidable equivalence risk; validate with the intended production plug/harness and a continuity fixture before release. Abnormal UART idle behavior also remains to be characterized.
- Exact ring-lug probe supplier/MPN remains open. Supplier must confirm continuous −40…+125°C measurement, R25 and beta tolerances/curve, sealing, cable insulation, lug encapsulation, strain relief, and termination. Existing JST PH J3/J4 are only −25…+85°C and are prohibited where the connector sees 125°C; production must use a verified ≥125°C connector/contact pair or a hardwired high-temperature pigtail that moves the connector into a ≤85°C zone.
Change Notes
- Selected ESP32-C3-WROOM-02-N4, LMR36506MSC3RPERQ1, SHT41I-AD1B-R2, TPL5010DDCR, USBLC6-2SC6.
- Full canonical schematic connectivity added for power, USB, MCU, UART, watchdog, humidity sensor, dual NTC channels, controls, protection, and indication.
- Firmware Starter, Board Bring-Up Plan, Design Notes/power budget, and FCC/CE draft created.
- Replaced provisional JST PH J1 with CAX HY2.0-4P-WT (C722729), retained the protected UART/pack nets, and enforced board order 1 GND, 2 module RX/BMS TX, 3 module TX/BMS RX, 4 VDD/full-pack.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes
