Unconnected Pins on U1
VDDA_PLL.Table
| Pin on U1 | Net | Netlist observation | Datasheet evidence | Verdict |
|---|---|---|---|---|
VDDA_PLL | Net 110 | Connected only to local RC/filter parts, but not to a driven power rail. ERC also reports “Power input not driven: U1:VDDA_PLL”. | Datasheet pin listing identifies VDDA_PLL as PLL Analog VDD Supply. That means it is a supply pin, not a leave-floating signal. | Should be connected to the PLL analog supply source. |
TEST2 | Net 28 | Only U1:TEST2 is on this net, so it is floating. | Datasheet snippet states: “The state of the TEST1, TEST2, and nRESETIN signals determines the operating mode entered at Power-on Reset.” A mode-select pin must not float. | Should not be left floating. It needs a defined level per the datasheet’s boot/test-mode requirements. |
TEST1 | Net 29 | Not floating internally, but it only goes off-chip and I do not see any local pull-up/pull-down ensuring a default state. | Same datasheet statement as above: TEST1, TEST2, and nRESETIN determine startup mode. | Potential issue if the external source can ever float during reset. |
Various muxed GPIO / LCD / ADC pins such as PB2/nCS3, PE5/SSPRX, PG0/LCDPS, PG1/LCDCLS, PG2/LCDDSPLEN/LCDREV, PG4/LCDVEEEN/LCDMOD, AN6/PJ1, AN8/PJ3, AN9/PJ5, AN4/PJ6, PF4/..., PD1/INT1 | single-pin nets | These appear intentionally unused in the current netlist. | For multifunction I/O, whether they “should” be tied depends on how firmware configures them. | Not automatically wrong, but worth checking against the datasheet’s unused-input guidance. |
VDDA_PLLTEST2TEST1 startup biasingWelcome 👋
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