Unconnected Pins on U1

flux

Yes. The clearest one is U1 pin VDDA_PLL.
U1 pins that look wrong or risky

Table

Pin on U1NetNetlist observationDatasheet evidenceVerdict
VDDA_PLLNet 110Connected only to local RC/filter parts, but not to a driven power rail. ERC also reports “Power input not driven: U1:VDDA_PLL”.Datasheet pin listing identifies VDDA_PLL as PLL Analog VDD Supply. That means it is a supply pin, not a leave-floating signal.Should be connected to the PLL analog supply source.
TEST2Net 28Only U1:TEST2 is on this net, so it is floating.Datasheet snippet states: “The state of the TEST1, TEST2, and nRESETIN signals determines the operating mode entered at Power-on Reset.” A mode-select pin must not float.Should not be left floating. It needs a defined level per the datasheet’s boot/test-mode requirements.
TEST1Net 29Not floating internally, but it only goes off-chip and I do not see any local pull-up/pull-down ensuring a default state.Same datasheet statement as above: TEST1, TEST2, and nRESETIN determine startup mode.Potential issue if the external source can ever float during reset.
Various muxed GPIO / LCD / ADC pins such as PB2/nCS3, PE5/SSPRX, PG0/LCDPS, PG1/LCDCLS, PG2/LCDDSPLEN/LCDREV, PG4/LCDVEEEN/LCDMOD, AN6/PJ1, AN8/PJ3, AN9/PJ5, AN4/PJ6, PF4/..., PD1/INT1single-pin netsThese appear intentionally unused in the current netlist.For multifunction I/O, whether they “should” be tied depends on how firmware configures them.Not automatically wrong, but worth checking against the datasheet’s unused-input guidance.
Bottom line
  • Definitely fix: VDDA_PLL
  • Very likely fix: TEST2
  • Review carefully: TEST1 startup biasing
  • The other single-pin multifunction I/Os are not necessarily errors; they may be intentionally unused.
If you want, I can do a second pass and produce a complete list of every U1 pin on a one-pin net, grouped into:
  • definitely must connect
  • should be biased
  • safe to leave unused depending on firmware
List all one-pin nets
Fix startup pins
Check other power pins
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