Simulation Project Setup
0:04
Work done
- Reviewed the Design Specification and extracted the locked behaviors, operating assumptions, and unresolved gaps that affect simulation setup.
- Used those requirements to populate the existing Simulation & Test Results document as a living record linked back to the design spec.
- Ran and documented initial architecture-level simulations for solar qualification, USB input budget, source switching priority, battery-charging behavior, boosted-output modes, and the always-on 3.3 V rail.
- Added plots, result tables, observations, issues, and reusable insights to the results document, including first-pass implications for USB current budget, solar qualification thresholds, and required source-priority behavior.
Success criteria review
- ✅ A Simulation & Test Results document exists and is linked to the Design Specification.
- ✅ Initial simulation data for solar, USB, source switching, battery charging, boost behavior, and 3.3 V regulation were captured and stored in the results document.
- ✅ The document now includes clear sectioning for plots, tables, observations, issues, design implications, and reusable insights for future iterations.
Next steps
The main follow-up is a second simulation pass using a more detailed solar I-V model and dedicated converter-level simulations for the CN3063/RT8059/MT3608 stages. I can do that next if you want to tighten the architecture before schematic capture.
Create results doc
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Simulation & Test Results
Linked design spec: Design Specification
1. Scope and status
This is a living document for simulation outputs, measurements, observations, issues, and reusable insights for the Low-Power Embedded Power Management Board 2276.
Locked behaviors from the design specification
- Inputs: solar panel, 1S LiPo battery, and USB-C input
- USB has priority over solar when both are present
- External power should run the system directly when available
- Battery charging is secondary to maintaining system load
- 3.3 V rail must remain available whenever any valid source exists
- 5 V and 12 V boosted outputs are mutually exclusive and manually selected
Known gaps impacting simulation fidelity
- Exact USB-C feature level is not locked beyond 5 V sink behavior
- Solar usable threshold and MPP operating point are not defined beyond Voc about 6 V
- Exact charger/power-path topology is not locked
- Acceptable interruption/transient during live 5 V / 12 V switching is not defined
- Downstream ripple, startup, and sequencing limits are not yet specified
- No schematic is present yet, so initial simulations use architecture-level behavioral models aligned to the design specification
2. Simulation organization
Each subsystem section should contain:
- Assumptions and model
- Test cases
- Plots
- Tables
- Observations
- Issues / open questions
- Reusable insights
3. Solar input
Assumptions and model
- Solar source modeled first as an architecture-level source aligned to the design spec: 6 W panel, Voc about 6 V, nominal MPP approximated near 5 V / 1 A.
- Qualification objective: determine when solar can sustain the always-on 3.3 V / 500 mA rail and when any battery-charging margin remains.
- Behavioral conclusion should be treated as first-pass architecture guidance because panel MPP is not yet locked in the specification.
Test cases
- DC sweep of available panel voltage from 3.5 V to 6.0 V
- Startup transient checks at 4.0 V, 4.25 V, and 4.5 V available panel conditions
- Shared load model includes the always-on 3.3 V rail with charger current only when source margin exists
Tables
Solar qualification summary
| Available panel condition | Final system voltage | Solar input power | Battery charge current | Interpretation |
|---|---|---|---|---|
| 4.0 V conservative startup | 3.431 V | 0.92 W | ~0 A | Briefly crosses threshold then collapses |
| 4.25 V conservative startup | 3.427 V | 1.95 W | ~0 A | Still collapses after startup |
| 4.5 V conservative DC | 3.646 V | 2.20 W | ~0 A | First clearly sustainable tested point |
| 5.0 V conservative DC | 4.063 V | 2.83 W | 21.8 mA | Small charging margin begins |
| 5.25 V conservative DC | 4.246 V | 3.30 W | 59.4 mA | Useful charging margin |
| 6.0 V conservative DC | 4.789 V | 4.95 W | 182 mA | Comfortable margin |
Plot
Image
Observations
- Minimum practical solar qualification from the first-pass model is about 4.5 V available panel voltage and about 2.2 W input power.
- Below about 5.0 V, the solar source may keep the always-on rail alive but provides essentially no meaningful charging margin.
- The unstable region is approximately 4.0 V to 4.25 V, where startup can briefly cross a UVLO-like threshold then fall back.
Issues / open questions
- The current result uses a Thevenin-style approximation rather than a measured panel I-V curve.
- The specification still lacks a locked MPP operating point and usable-threshold definition for the panel.
Design implications
- Set a hard minimum solar qualification threshold near 4.5 V for system sustain.
- If charging is expected, use a more conservative threshold of 5.0 V minimum, with 5.25 V preferred for useful charge current.
4. USB input
Assumptions and model
- USB-C modeled as a 5 V source with a 500 mA worst-case current budget, per the design specification.
- Cases checked: always-on 3.3 V / 500 mA rail only, plus boosted 5 V / 500 mA, and plus boosted 12 V / 100 mA.
- Charger control is reduced to zero whenever the USB input would exceed the current budget.
Test cases
- 3.3 V rail only
- 3.3 V rail + 5 V boost at 500 mA
- 3.3 V rail + 12 V boost at 100 mA
Tables
USB budget summary
| Condition | Steady USB current | Peak startup current | Charger forced off | Viable from 5 V / 500 mA USB? |
|---|---|---|---|---|
| 3.3 V rail only | 366.7 mA | 461.1 mA | No | Yes |
| 3.3 V + 5 V boost at 500 mA | 922.2 mA | 1.173 A | Yes | No |
| 3.3 V + 12 V boost at 100 mA | 633.3 mA | 1.328 A | Yes | No |
Plot
Image
Observations
- The always-on 3.3 V / 500 mA rail alone is feasible from default USB input, leaving about 133 mA of headroom.
- Either boosted-output operating mode exceeds the 500 mA USB budget even after charge current is reduced to zero.
- Startup peaks above 1 A in both boosted modes suggest likely port foldback or startup failure on a strict 500 mA USB source.
Issues / open questions
- The specification requests desired current negotiation capability but does not yet lock the USB-C feature level.
- No hard input-current limiting or staged startup architecture is yet defined.
Design implications
- The board cannot support worst-case 3.3 V + boosted rail operation from a default 5 V / 500 mA USB source alone.
- One or more of the following will be required: higher negotiated USB current, battery assist, reduced simultaneous load, or staged/soft-start boost activation.
5. Source switching
Assumptions and model
- Three-source power-path model: USB 5 V, solar source near 5 V, and a 1S LiPo path.
- USB is given explicit priority control so solar is disconnected or blocked when USB is present.
- Battery fallback is enabled only when external sources are absent or insufficient.
Test cases
- Solar only
- USB inserted while solar remains connected
- USB removed while solar remains connected
- Both externals removed with battery at 4.2 V and 3.3 V cases
- Comparison run with flawed unblocked solar branch
Tables
Source priority summary
| Case | Key result |
|---|---|
| Solar only | SYS about 4.317 V |
| USB present with proper priority path | SYS about 4.524 V, solar current effectively 0 A |
| USB unplug to solar | About 207 mV expected level shift, essentially no extra glitch |
| External loss to full battery | SYS about 3.854 V |
| External loss to depleted battery | SYS about 2.968 V |
| Flawed unblocked solar branch with USB present | Solar still contributes about 231 mA while USB contributes only about 2 mA |
Plots
Image
Image
Observations
- USB priority is achieved in the controlled architecture: solar contribution with USB present is effectively zero.
- Plug-in and unplug events are essentially glitch-free; observed transitions are mostly expected DC level shifts between sources.
- Without proper ideal-diode or PFET control, USB presence alone does not dominate the rail and source contention occurs.
Issues / open questions
- The exact source-selection implementation is not yet locked.
- The current first-pass simulation validates priority behavior but not the final hardware mux component choice.
Design implications
- A blocked or actively disconnected solar branch is required ahead of the charger and/or system path.
- The source-priority stage must explicitly prevent solar contribution while USB is present.
6. Battery charging
Assumptions and device facts
- Preferred starting charger is CN3063 from the design specification.
- Datasheet facts gathered for initial validation:
- Input supply range 4.4 V to 6 V
- UVLO approximately 3.7 V to 3.9 V
- Preset float regulation 4.2 V with 1% accuracy
- Programmable charge current up to 600 mA
- 500 mA charge current uses about 3.6 kΩ on ISET
- Internal thermal regulation reduces charge current near 115 C junction limit
- Sleep-mode battery drain less than 3 uA when input is removed
Test interpretation from initial simulations
- In the solar qualification runs, charge current remains effectively zero near the minimum system-sustain threshold and only becomes useful above about 5.25 V source availability.
- In the USB input runs, the charger must be disabled whenever boosted loads are active under the default 500 mA USB budget.
Tables
Charging behavior implications
| Source condition | Charging result |
|---|---|
| Solar near minimum sustain threshold | No meaningful charging margin |
| Solar at about 5.0 V available | Small charge current begins |
| Solar at about 5.25 V available | Useful charging current begins |
| USB with 3.3 V rail only | Charging may remain enabled |
| USB with boosted output active | Charging must reduce to zero under 500 mA budget |
Observations
- The CN3063 is well aligned with the specified 4.4 V to 6 V source range and is explicitly intended for solar-powered systems.
- However, the design specification requires system-load priority and seamless external-source operation, which is a stronger architecture requirement than simple charge-only behavior.
- Because the project is still architecture-only, the first-pass conclusion is that charger behavior is acceptable only if upstream source qualification and downstream power-path/load-sharing are resolved explicitly.
Issues / open questions
- The exact power-path strategy is not yet locked, and that affects whether a charge-only architecture is acceptable.
- Battery protection remains required by the specification and is not yet modeled in detail.
Design implications
- Keep conservative charge behavior as specified.
- If the board must remain continuously operational while charging and during source transitions, the eventual architecture may need more than a bare charge-only implementation.
7. Boost mode
Assumptions and device facts
- Preferred starting boost IC is MT3608L / MT3608 family per the specification.
- Library data confirms the family is intended for 2 V to 24 V input and adjustable output, making 5 V and 12 V targets architecturally plausible from a 1S LiPo source.
- Datasheet extraction was not available from the selected library entry, so first-pass evaluation here is based on architecture-level simulation and library metadata rather than detailed pin-level device behavior.
Test cases
- Boosted 5 V / 500 mA while the always-on 3.3 V / 500 mA rail is active
- Boosted 12 V / 100 mA while the always-on 3.3 V / 500 mA rail is active
Tables
Boost mode viability from default USB input
| Boost mode | Steady USB current | Peak startup current | Viable from 5 V / 500 mA USB? |
|---|---|---|---|
| 5 V / 500 mA | 922.2 mA | 1.173 A | No |
| 12 V / 100 mA | 633.3 mA | 1.328 A | No |
Observations
- Both boosted modes are architecturally possible from battery/external power in principle, but not from default USB 5 V / 500 mA while the 3.3 V / 500 mA rail is also fully loaded.
- The 12 V / 100 mA case shows lower steady current than the 5 V / 500 mA case, but worse startup surge because of the higher output energy step.
Issues / open questions
- The specification prefers live switching between 5 V and 12 V, but acceptable transition interruption and output blanking behavior are still undefined.
- Final output-selection topology is still open.
Design implications
- Live mode switching should not be assumed safe without explicit transition control, output discharge, or interlock behavior.
- Boost enable should likely be staged or inhibited during USB-limited operation.
8. 3.3 V buck regulation
Assumptions and device facts
- Preferred starting regulator is RT8059.
- Datasheet facts gathered for first-pass validation:
- Input range 2.8 V to 5.5 V
- Fixed-frequency PWM, 1.5 MHz typical
- Reference voltage 0.6 V typical
- Adjustable output examples include 3.3 V with 249 kΩ / 54.9 kΩ feedback values
- Typical output current capability 1 A
- Typical current limit about 1.5 A
- Typical quiescent current about 78 uA
- Shutdown current about 0.1 uA typical
- Soft-start supported via the IC
Derived load target
- 3.3 V rail target is 500 mA, equal to 1.65 W output load.
Initial validation status
- Architecture-level simulations treated the 3.3 V rail as an always-on converter path and showed:
- It is supportable from USB-only operation within the 500 mA input budget when no boost rail is enabled.
- It becomes the baseline load that dominates solar qualification and USB budget decisions.
- Based on datasheet range, the RT8059 can regulate from nominal LiPo conditions and 5 V-class external rails, but detailed ripple and transient waveforms remain to be validated in a dedicated converter-level run.
Observations
- The regulator’s 2.8 V to 5.5 V operating range fits the intended source domain well.
- At the required 500 mA continuous load, this stage is central to overall input-budget feasibility.
Issues / open questions
- Dedicated converter-level simulation is still needed for ripple, load-step response, dropout margin near low battery, and thermal behavior.
- The specification says the 3.3 V rail must remain available whenever any valid source exists; that makes low-battery dropout behavior especially important.
Design implications
- The RT8059 remains a plausible starting point for the 3.3 V rail.
- The next simulation pass should focus specifically on regulation quality, startup, and low-input margin.
9. Reusable insights
Initial reusable insights
- The current specification is strong enough to support useful architecture-level simulation even before a schematic exists.
- The default USB 5 V / 500 mA budget is a dominant system constraint and should be treated as a first-order design limiter.
- Solar qualification cannot be defined from Voc alone; a usable threshold and realistic MPP operating point must be added to the design specification.
- The always-on 3.3 V rail materially constrains both charging margin and boosted-output availability.
- Source priority cannot be treated as implicit diode OR-ing; explicit priority control or blocking is required to guarantee USB over solar behavior.
Recommended updates to the design specification
- Lock the minimum acceptable solar qualification rule, distinguishing:
- sustain-only threshold
- sustain-plus-charge threshold
- Lock the USB-C feature level, especially whether current negotiation above default USB current is required.
- Define acceptable interruption and transient behavior for live 5 V / 12 V mode switching.
- Add explicit limits for 3.3 V ripple, startup time, and brownout tolerance.
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