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PCB Design for Low-Power Sensor System

flux

3:14

Accessing knowledge base.

Running design review.

Analyzing the schematic.

Here’s what still needs correction before you can create the PCB, plus practical workarounds where needed.
Critical blockers to fix first
  • Power net short into ground:
    • GND contains IC1, U2, U2, and U3 (fatal).
    • Fix:
      • Create a 1V8 net. Connect U2 → 1V8 → IC1, U3, temp sensor VDD.
      • Rewire decouplers so each cap has P1 to its supply (1V8 or VIN) and P2 to GND. Right now many P1 pins are on GND.
      • Ensure U2 is ONLY tied to the piezo input path (via J1), not to GND.
  • RF airwire:
    • DRC shows an airwire between IC1 and J2. You must hand-route this 50 Ω trace and add the via-fence/keepout.
  • TIA and I2C connectivity gaps:
    • Airwires: R6–R7–R8 junction not fully connected; U3 not actually tied to 1V8; IC1/IC1 to pull-ups show missing routes.
  • Temperature sensor part mismatch:
    • U4 is TT8M2TR (not STTS22H). Replace with STTS22H (preferred) or TMP117, then wire VDD to 1V8, GND to GND, SDA/SCL to IC1/IC1.
  • Missing MPNs for generics:
    • DRC “Manufacturer Part Number” errors on nearly all generics (R10, R11, C18, C19, C20, C21, C22, C23, etc.). Replace each with a real library part to clear manufacturing checks.
High-priority corrections (guided by best practices)
  • Decoupling (authoritative KB):
    • Use a typical capacitor combo “100 nF + 1 µF + 10 µF” per rail for high/low-frequency coverage and place 100 nF within 5 mm of each VDD/GND pair.
    • Apply to: IC1 with C18/C19 + a bulk (e.g., C8 or C17); U2 with C20/C21 and C22/C23; U3 with a local 100 nF.
  • I2C pull-ups (authoritative KB):
    • Base value on bus capacitance (spec max is “400 pF”) and 100 kHz. Lower resistance improves edge rates but increases sink/idle current. At 1.8 V, typical starting values are 4.7 kΩ for short, low-capacitance buses; move to 2.2 kΩ if the layout or cable adds capacitance. Remember idle current is VDD/Rpu continuously.
    • Action: Replace R10, R11 with real 1.8 V pull-ups (e.g., 4.7 kΩ 0603) tied to 1V8, not GND.
  • Ground/returns (authoritative KB):
    • Prevent switching ground bounce from coupling into the TIA by ensuring the return path for the TIA around U3 is not shared with U2’s switching loop. Prefer a continuous ground plane; steer returns using placement and stitching, guard sensitive nodes, and avoid hard split planes unless absolutely required.
RF path to finish
  • Route the RF net:
    • Hand-route IC1 → J2 straight and short on the top layer over a continuous ground reference layer. Add a via-fence along both sides of the trace.
  • Keepouts:
    • Add a keepout around the RF pad/trace (2 mm around the launch you specified). Single-layer is fine; use a Zone if you later need multi-layer cutouts.
Schematic-specific fixes (seen in current nets)
  • Move these pins off GND and onto proper nets:
    • IC1 → 1V8
    • U3 → 1V8
    • U2 → 1V8
    • U2 → piezo input only (from J1)
    • Ensure each decoupler P1 goes to its supply net, and P2 goes to GND.
  • TIA network:
    • The R6/R7/R8 junction is unrouted. Complete the inverting node connections, and connect the TIA output through R9/C7 to the ADC pin on IC1.
    • Values currently read as 500 Ω. For pA–µA work, populate at least one high-value option (1 MΩ or 10 MΩ) footprint; use a guard ring around the inverting input. Consider switching the feedback legs with a low-leakage analog switch rather than GPIO, if leakage becomes a problem.
  • Harvester configuration:
    • Strap U2 for a 1.8 V output setting; wire PGOOD if used. Size/attach the output storage cap per datasheet on CAP/VOUT (you already have C11/C5, verify values).
Layout readiness issues
  • Board outline is huge (about 1005 × 1652 mm). Shrink to a realistic footprint target for your device (for example 20 × 20 mm as a starting point) to shorten traces and reduce parasitics before routing.
  • Ensure Layer 2 is a continuous ground plane beneath the RF trace and the TIA. Stitch ground around the RF and around the TIA guard area.
Workarounds if something isn’t solvable immediately
  • Temp sensor availability:
    • If STTS22H cannot be placed now, use TMP117 temporarily. Both are I2C at 1.8 V; keep the same pull-ups and decoupling.
  • TIA gain switching/leakage risk:
    • If GPIO-controlled ladder injection is problematic, switch to a low-leakage analog switch (e.g., search: TS5A3359 or ADG819) to select feedback resistors without loading the inverting node.
  • 50 Ω constraint:
    • If you can’t compute exact CPWG width with your current stackup, keep the RF trace as short/straight as possible over a solid ground plane, use a conservative keepout, and match the connector launch with tight ground via fencing. You can refine trace width later with an impedance calculator without upsetting most of the layout.
DRC/Manufacturing to close out
  • Route all airwires flagged in DRC:
    • [IC1:RFIOP] ↔ [J2:1], [R6:P2]–[R7:P2]–[R8:P2], [IC1:GPIO03] ↔ [R11:P2], [U3:V+] ↔ 1V8 from [U2:VOUT], etc.
  • Replace generics with real library parts (assign MPNs) for resistors and capacitors:
    • Examples to search:
      • 100 nF 0603 10 V X7R: 100nF Capacitor
      • 1 µF 0603 10 V X5R: 1uF Capacitor
      • 10 µF 0603 6.3 V X5R: 10uF Capacitor
      • I2C pull-ups 4.7 kΩ 0603 1%: 4.7k Resistor
      • High-value TIA feedback (1 MΩ/10 MΩ): 1M Resistor, 10M Resistor
Would you like me to prepare a small, ordered fix list you can run (power net de-merge → sensor replacement → I2C pull-up values → TIA wiring → RF route → MPN updates)? I can also create a plan to apply these changes automatically and then re-run DRC.
Generate fix list
Split power nets
Search decoupling parts
Add RF keepout
Find temp sensor
188 days
flits101

flits101

Yes, please outline the ordered fix list you mentioned.
188 days

flux

0:32

Sorry, something went wrong. Please try again later.
188 days
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    Alert Rose TARDIS

    Alert Rose TARDIS thumbnail
    Ultra-Low-Power 1.8V Piezoelectric Energy Harvesting RF Sensor Node with Apollo3 Blue, LTC3588-1, STTS22H, and OPA333

    Properties

    1642.1

    mm

    0.6

    mm

    Standard 4 Layer

    0.3

    mm

    U3, R6, R7, R8, C7, C4

    Diagram
    


  
    
  
  
    
  





Piezo
LTC3588-1
MCU

    0.2

    mm

    1652.1

    mm

    J1, U2, C5, C6, C11, C17

    1005.2

    mm

    1.8

    V

    1652.1

    mm

    0.2

    mm

    995.2

    mm

    Pricing & Availability

    Distributor

    Qty 1

    Controls

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