ESP32 Flex Sensor Board Design
0:04
Work done
- Removed duplicate legacy schematic blocks and kept a single production path built around IC2, U5, J9, U6, U3, and U7
- Removed alternate/duplicate parts U1, U2, J1, IC1, J2, U4, U8, J7, J8, SW1, SW2, J4, J5, and J6
- Normalized USB net names to USB_DP and USB_DN, retained the 3-pin haptic connector scheme on J11 and J12, and added explicit no-connect markers for intentionally unused pins on IC2, U5, U7, U3, and J9
- Verified key power and interface rails: VBUS -> U5 -> VSYS -> U3 -> 3V3, battery rail VBAT to J10, USB native data from J9 through U6 to IC2, and boot/reset pull networks on SW3, SW4, R17, and R8
- Set the layout to 160 mm x 100 mm, 4-layer, with inner layer 2 as ground plane and inner layer 3 as a power-oriented plane, plus baseline board rules of 0.15 mm minimum trace width, 0.15 mm minimum keep-out, and 0.2 mm board inset margin
- Updated and saved project notes in Design Notes
Success criteria review
- ✅ The schematic was substantially cleaned up and duplicate major circuits were removed
- ✅ Power, USB, and ESP32 boot/reset circuitry were reviewed and consolidated into a single retained implementation
- ✅ Production MPN metadata was improved for key ICs including U3 and U7, and all current parts have footprints assigned
- ✅ The PCB layout size, stackup, and core board rules are now defined
- ❌ The layout is not yet fully routed: DRC still reports 82 airwire errors
- ❌ ERC still reports unresolved floating capacitor pins on C1, C7, C8, and C16
- ❌ I could not complete placement optimization or trace routing because the available toolset in this run does not include a placement or routing mutation tool, so I cannot finish the remaining PCB connectivity from here
Next steps
The design is materially cleaner and constrained, but it is not yet production-ready because routing and a few remaining schematic cleanup items are still open. If placement and auto-routing tools are made available in a follow-up run, I can finish the remaining airwires, resolve the last floating caps, and close the final ERC/DRC gap.
Clean up duplicates
Review critical circuits
Fix ERC/DRC issues
12 days
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Design Notes
ESP32 Flex Haptic Board production cleanup
- Removed duplicate legacy schematic blocks so the retained production path uses IC2, U5, J9, U6, U3, and U7.
- Removed duplicate legacy alternates: U1, duplicate charger U2, duplicate USB-C J1, duplicate IMU IC1, alternate battery connector J2, duplicate ESD U4, duplicate buttons SW1 and SW2, duplicate flex connectors J4, J5, J6, alternate regulator U8, and alternate haptic headers J7, J8.
- Normalized native USB net names to USB_DP and USB_DN.
- Kept 3-pin haptic module connectors J11 and J12 with pinout VCC, GND, DATA.
- Marked intentionally unused pins on the USB-C SBU pins, IMU auxiliary/interrupt pins, unused ESP32 GPIOs, charger status pins, and regulator NC to suppress non-functional ERC noise.
Layout constraints
- Finalized layout size to 160 mm x 100 mm rectangle with 3 mm corner radius.
- Retained 4-layer stackup and assigned inner layer 2 as the ground plane, inner layer 3 as a power-oriented plane in the custom stackup.
- Applied baseline manufacturable constraints: 0.15 mm minimum trace width, 0.15 mm minimum keep-out, and 0.2 mm board inset margin.
Remaining risk items
- Airwires still need routing completion in the PCB layout.
- Some passives and earlier removed-component references may still appear in stale ERC/DRC or legacy nets until fully revalidated in layout context.
- U3 is usable and stocked, but should still be watched for lifecycle preference in future sourcing reviews.
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