PCB Routing Issues

flux

Connectors XLR
  • J2 — entrada micròfon
    • XLR_MIC_HOT_P2
    • XLR_MIC_COLD_P3
    • USB_SHIELD_CHASSIS
  • J4 — sortida esquerra
    • LINE_OUT_L_HOT_P2
    • LINE_OUT_L_COLD_P3
    • USB_SHIELD_CHASSIS
  • J5 — sortida dreta
    • LINE_OUT_R_HOT_P2
    • LINE_OUT_R_COLD_P3
    • USB_SHIELD_CHASSIS
Drivers de línia
  • U14 — DRV134, canal esquerre
    • Entrada: DAC_L_TO_LINE_DRIVER
    • Sortides: LINE_OUT_L_HOT_P2, LINE_OUT_L_COLD_P3
    • Alimentació: +15VA, -15VA, GND 3
  • U15 — DRV134, canal dret
    • Entrada: DAC_R_TO_LINE_DRIVER
    • Sortides: LINE_OUT_R_HOT_P2, LINE_OUT_R_COLD_P3
    • Alimentació: +15VA, -15VA, GND 3
Consulta feta exclusivament sobre la netlist, sense geometria, routing ni DRC.
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Routing Inventory
Scope and method
This inventory was produced using only lightweight schematic netlist queries. No PCB geometry, routing scan, spatial search, or DRC was used. Therefore, it identifies the circuits and endpoints in the USB-C/PD and MCU blocks, but it does not by itself prove whether each PCB connection is already routed.
USB-C/PD ↔ MCU control circuits
These nets connect U1 (STUSB4500 USB-C PD controller) directly to U17 (MCU) and are the primary control-signal routing worklist:

Table

NetFunctionSelected endpoints
I2C_PD_SCLPD-controller I2C clockU1 ↔ U17
I2C_PD_SDAPD-controller I2C dataU1 ↔ U17
STUSB_RESETMCU-controlled STUSB4500 resetU1 ↔ U17
PD_ALERT_N_TO_MCUPD interrupt/alert, open drainU1 ↔ U17
PD_ATTACH_TO_MCUCable-attach status, open drainU1 ↔ U17
PD_PDO2_OK_TO_MCUPDO2 status, open drainU1 ↔ U17
PD_PDO3_OK_TO_MCUPDO3 status, open drainU1 ↔ U17
USB_C_ORIENTATION_TO_MCUPlug orientation status, open drainU1 ↔ U17
PD_SNK_EN_STATUS_TO_MCUSink-enable/status output, open drainU1 ↔ U17
The STUSB4500 status outputs above require pull-ups to a valid MCU logic rail. PD_SNK_EN_STATUS_TO_MCU must be configured as an MCU input and never driven by firmware. STUSB_RESET is active high with an internal pull-down; its default state must remain low.
USB-C/PD local circuits

Table

NetFunction
USB_CC1USB-C CC1 path
USB_CC2USB-C CC2 path
VBUS_ENTRY_15VNegotiated/input VBUS supply path
VBUS_SENSE_DISCHVBUS sensing/discharge control
VBUS_PD_DISCHPD VBUS discharge path
STUSB_ADDR0STUSB4500 address strap
STUSB_ADDR1STUSB4500 address strap
STUSB_VREG_1V2Internal 1.2 V regulator support
STUSB_VREG_2V7Internal 2.7 V regulator support
MCU supervision and power-status circuits

Table

NetFunction
EFUSE_FAULT_N_TO_MCUeFuse fault status
EFUSE_PGOOD_TO_MCUeFuse power-good status
PGOOD_3V3_DIGDigital 3.3 V power-good
PGOOD_XMOS_1V0XMOS 1.0 V power-good
MCU_NRSTMCU hardware reset
MCU_BOOT0MCU boot-mode strap
MCU_SWDIOSWD programming/debug data
MCU_SWCLKSWD programming/debug clock
MCU_SWOSWD trace output
MCU peripheral-control circuits found
Audio and preamplifier control
  • ADC_PDN_TO_MCU
  • ADC_OVF_TO_MCU
  • SPI_PREAMP_SCLK
  • SPI_PREAMP_MOSI
  • SPI_PREAMP_MISO
  • SPI_PREAMP_CS_N
  • PREAMP_GAIN_RST_N_TO_MCU
  • PREAMP_GAIN_BSY_TO_MCU
  • LOOPBACK_EN
Phantom-power control
  • PHANTOM_EN_TO_MCU
  • PHANTOM_MON_ADC_TO_MCU
Encoder and LED-ring interface
  • UI_ENC_A
  • UI_ENC_B
  • UI_ENC_SW
  • LED_RING_DATA
  • LED_RING_CLK
  • LED_RING_LATCH
  • LED_RING_OE
Supply/ground nets appearing in the selected blocks
  • GND
  • GND 2
  • GND 3
  • U9 VDDIOL - U9 VDDIOR
The unusual supply-net name U9 VDDIOL - U9 VDDIOR includes U1 and multiple U17 supply pins in the returned connectivity. It should be reviewed later as a focused net-identity/power-domain check before power routing.
  1. Manually complete I2C_PD_SCL, I2C_PD_SDA, and STUSB_RESET.
  2. Route the six remaining U1↔U17 status/control nets as one small low-speed group.
  3. Route SWD/debug and MCU boot/reset nets.
  4. Route preamplifier SPI and control signals.
  5. Route encoder and LED-ring signals.
  6. Route phantom-control and monitoring signals.
  7. Review the unusual U1/U17 supply-net identity before routing power or ground.
XMOS block (U9)
This section was produced from a netlist-only query limited to U9. Nets shown with one selected U9 pin are not necessarily electrically incomplete; the other endpoints were outside the selected-component query.
USB interface

Table

NetFunction
USB_DPUSB high-speed data D+
USB_DNUSB high-speed data D−
XMOS_USB_RTUNEUSB PHY reference-tuning resistor connection
XMOS_USB_VBUS_SENSEUSB VBUS detection input
Clock inputs

Table

NetFunction
XMOS_CLK_24MDedicated 24 MHz XMOS/USB reference clock
AUDIO_XO_22M5792_TO_XMOS44.1 kHz-family audio clock source
AUDIO_XO_24M576_TO_XMOS48 kHz-family audio clock source
The 22.5792 MHz and 24.576 MHz oscillators are audio MCLK sources, not substitutes for the dedicated 24 MHz USB PLL reference.
ADC and DAC digital-audio interface

Table

NetDirection/functionKnown status
ADC_MCLK_FROM_XMOSXMOS → ADC master clockManually routed
ADC_LRCLK_FROM_XMOSXMOS → ADC frame clockManually routed
ADC_BCLK_FROM_XMOSXMOS → ADC bit clockManually routed
ADC_SDTO1_TO_XMOSADC → XMOS serial data 1Manually routed
ADC_SDTO2_TO_XMOSADC → XMOS serial data 2Manually routed
DAC_DIN_FROM_XMOSXMOS → DAC serial audio dataRouting status not established by netlist
ADC_OVF_TO_MCUADC overflow/status path also appearing at U9Routing status not established by netlist
QSPI boot-flash interface

Table

NetFunction
XMOS_QSPI_CS_NFlash chip select
XMOS_QSPI_CLKFlash clock
XMOS_QSPI_D0_BOOT_LOWQSPI data/boot strap D0
XMOS_QSPI_D1_BOOT_LOWQSPI data/boot strap D1
XMOS_QSPI_D2_BOOT_LOWQSPI data/boot strap D2
XMOS_QSPI_D3_HOLD_NQSPI data/HOLD# D3
Treat the QSPI pins as boot straps first. Avoid pull-ups on X0D04/X0D05/X0D06, especially the IO2/WP# function; retain the CS# pull-up and weak pull-down footprints on strap/data pins.
Reset and JTAG/debug
  • XMOS_RST_N
  • XMOS_TMS
  • XMOS_TCK
  • XMOS_TDI
  • XMOS_TDO
XMOS supply domains
  • XMOS_1V0_CORE — 11 selected U9 core-supply pins
  • XMOS_PLL_1V0 — PLL 1.0 V supply
  • U9 VDDIOL - U9 VDDIOR — 6 selected U9 I/O-supply pins
  • GND 3 — selected XMOS ground pins
The net U9 VDDIOL - U9 VDDIOR also appeared in the previous U1/U17 query. Its exact power-domain membership should be checked with a separate focused net-identity query before routing power.
XMOS routing worklist
  1. Preserve the five manually routed ADC/I2S nets.
  2. Route and verify USB_DP/USB_DN as the dedicated USB differential pair.
  3. Route XMOS_CLK_24M with a short, clean clock path.
  4. Route both audio-family oscillator inputs independently; do not join them together.
  5. Route the QSPI flash bus as a compact local group while respecting boot-strap requirements.
  6. Route XMOS_RST_N and JTAG signals.
  7. Route DAC_DIN_FROM_XMOS and clarify the ADC_OVF_TO_MCU endpoint relationship.
  8. Review the I/O-supply net identity before power/ground routing.
ADC, ADC driver, and DAC blocks
This section was produced using netlist-only queries limited to U7, U8, and U13. U7 is the ADC, U8 is the fully differential ADC input driver, and U13 is the DAC. A one-pin result means only one selected component was queried; it does not prove the overall net is incomplete.
ADC U7 — digital audio and control

Table

NetFunctionKnown status
ADC_MCLK_FROM_XMOSADC master clockManually routed
ADC_LRCLK_FROM_XMOSADC frame clockManually routed
ADC_BCLK_FROM_XMOSADC bit clockManually routed
ADC_SDTO1_TO_XMOSADC serial-data channel 1Manually routed
ADC_SDTO2_TO_XMOSADC serial-data channel 2Manually routed
ADC_PDN_TO_MCUADC power-down controlRouting status not established by netlist
ADC_OVF_TO_MCUADC overflow/status outputRouting status not established by netlist
ADC_LDOE_STRAPADC internal-LDO configuration strapLocal strap circuit
ADC_TEST_STRAPADC test/mode strapLocal strap circuit
For multi-rate operation across both 44.1 kHz and 48 kHz sample-rate families, the ADC clock-mode straps must implement the automatic clock mode rather than assuming a fixed 512fs configuration.
ADC U7 — analog inputs and supplies

Table

NetFunction
ADC_AIN1P / ADC_AIN1NADC differential input channel 1
ADC_AIN2P / ADC_AIN2NADC differential input channel 2
ADC_VDD18_COREADC 1.8 V core supply
5VA_ADCClean ADC analog 5 V supply
U9 VDDIOL - U9 VDDIORDigital I/O supply net currently shared by naming/identity
GND 3ADC ground domain in the returned netlist
Unused AK5574-family analog input pairs must remain open and should be powered down where possible; do not tie unused AIN pairs to a common-mode node.
Fully differential ADC driver U8

Table

NetFunction
ADC_DRV_IN_P / ADC_DRV_IN_NDifferential driver input
ADC_DRV_OUT_P / ADC_DRV_OUT_NDifferential output to ADC path
ADC_DRV_ENABLEDriver enable/control
ADC_VCM_2V5Driver common-mode reference
+15VA / -15VABipolar analog supplies
ADC_VCM_2V5 must be a low-noise, low-impedance source or buffered reference with local bypassing and stability isolation; it should not be driven by a simple passive divider.
DAC U13 — digital interface and outputs

Table

NetFunctionKnown status
DAC_DIN_FROM_XMOSXMOS-to-DAC serial audio dataRouting status not established by netlist
ADC_BCLK_FROM_XMOSShared audio bit clock into DACI2S net manually routed around U7/U9; DAC branch status not established
ADC_LRCLK_FROM_XMOSShared audio frame clock into DACI2S net manually routed around U7/U9; DAC branch status not established
DAC_L_RAWRaw left-channel analog outputRouting status not established by netlist
DAC_R_RAWRaw right-channel analog outputRouting status not established by netlist
DAC U13 — local supply and charge-pump support
  • DAC_CAPP
  • DAC_CAPM
  • DAC_VNEG
  • DAC_LDOO_1V8
  • U9 VDDIOL - U9 VDDIOR
  • GND 3
The DAC charge-pump and local-regulator nets should remain short local connections with their support capacitors placed and routed directly at U13.
ADC/DAC routing worklist
  1. Preserve the five manually routed ADC/XMOS I2S nets.
  2. Confirm and complete the BCLK/LRCLK branches from the existing routed trunks to DAC U13.
  3. Route DAC_DIN_FROM_XMOS.
  4. Route ADC_PDN_TO_MCU, ADC_OVF_TO_MCU, and ADC_DRV_ENABLE as a small low-speed control group.
  5. Complete U7 strap circuits ADC_LDOE_STRAP and ADC_TEST_STRAP locally.
  6. Route U8 differential input/output pairs symmetrically and keep ADC_VCM_2V5 quiet.
  7. Route DAC_L_RAW and DAC_R_RAW toward the analog-output stage, away from digital clocks.
  8. Complete DAC charge-pump/local-LDO support nets as short local connections.
  9. Review the reused U9 VDDIOL - U9 VDDIOR net identity before routing converter power.
Next inventory block
The next safe lightweight query should cover the microphone preamplifier and analog input/output stages without inspecting PCB geometry.

  • Scope and method

  • USB-C/PD ↔ MCU control circuits

  • USB-C/PD local circuits

  • MCU supervision and power-status circuits

  • MCU peripheral-control circuits found

  • Audio and preamplifier control

  • Phantom-power control

  • Encoder and LED-ring interface

  • Supply/ground nets appearing in the selected blocks

  • Recommended routing order

  • XMOS block (U9)

  • USB interface

  • Clock inputs

  • ADC and DAC digital-audio interface

  • QSPI boot-flash interface

  • Reset and JTAG/debug

  • XMOS supply domains

  • XMOS routing worklist

  • ADC, ADC driver, and DAC blocks

  • ADC U7 — digital audio and control

  • ADC U7 — analog inputs and supplies

  • Fully differential ADC driver U8

  • DAC U13 — digital interface and outputs

  • DAC U13 — local supply and charge-pump support

  • ADC/DAC routing worklist

  • Next inventory block

USB Measurement Audio Interface thumbnail
High-end 2-channel USB Audio Class 2.0 measurement interface for Smaart/REW use, with XMOS digital audio, isolated converter domain, smart encoder/LED UI, precision mic input, DAC line output, loopback ADC, phantom power, and protected USB-C power input.

Properties

Pricing & Availability

Distributor

Qty 1

Arrow

$55.08–$77.22

Digi-Key

$52.41

HQonline

$22.81–$25.31

LCSC

$186.05–$186.94

Mouser

$207.72

TME

$32.57

Verical

$81.64–$1,132.81

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