PCB Design for Bluetooth RC Car

Work done
  • Verified the layout is still 70 mm x 50 mm on a 4-layer stack and confirmed the current stack template is Standard 4 Layer.
  • Confirmed U1 is currently placed near the board interior, not at an edge, so the antenna rule is still violated.
  • Confirmed the schematic still has 20 floating ESP32 pins and that the existing No Connect component property on U1 is metadata only, not real schematic no-connect markers.
  • Confirmed DRC still reports 60 airwire errors.
  • Reviewed current placement of the power section around U3, U2, U4, C6, C7, C8, C9, L1, and D1.
Success criteria review
  • U1 is not yet positioned at the board edge with a strict 12 mm all-layer antenna keepout.
  • ❌ Unused ESP32 GPIO pins are not converted into real schematic no-connect markers, so ERC still reports 20 floating-pin errors.
  • ❌ All nets are not fully routed; DRC still reports 60 unrouted airwires.
  • ❌ I could not complete the requested buck/motor-driver placement optimization because the available tools in this session do not include a component-placement action.
  • ❌ Final ERC and DRC are not clean, so the design is not signoff-ready.
Next steps I’m blocked by missing write capabilities required for this exact task: there is no available tool in this session to place real schematic NC markers, no available placement tool to move U1 to the board edge and enforce the antenna keepout region, and no routing tool to finish the remaining airwires. If those edit capabilities are enabled, I can continue from the current verified blocker list immediately.
Fix ERC/DRC issues
Set ESP32 keepout
Mark unused GPIOs
Optimize power routing
Report unrouted nets
GND
U4 VIN - C7 P2
U2 AO2 - J1 P2
U1 3V3 - C2 P1
VCC_5V
J3 Center pin - C1 P1
U2 AO2 - J1 P2
U2 BO1 - J2 P1
J3 Center pin - C1 P1
U1 3V3 - C2 P1
U1 IO26 - U2 PWMB
U1 3V3 - C2 P1
U4 VIN - C7 P2
U1 IO12 - U2 BIN1
GND
U2 VM3 - C9 P1
U1 IO13 - U2 BIN2
U1 IO12 - U2 BIN1
C4 P2 - U4 VSS
U2 BO2 - J2 P2
U4 VIN - C7 P2
U2 PGND2 - U3 GND
U2 BO2 - J2 P2
C4 P2 - U4 VSS
U1 IO26 - U2 PWMB
U1 EN - R1 P2
U2 PGND2 - U3 GND
U3 FB - R2 P2
U2 VM3 - C9 P1
C4 P2 - U4 VSS
J3 Center pin - C1 P1
U2 AO1 - J1 P1
U2 AO1 - J1 P1
U1 EN - R1 P2
U2 PGND2 - U3 GND
U3 FB - R2 P2
U3 SW - L1 1
C4 P2 - U4 VSS
U1 IO14 - U2 AIN2
U1 3V3 - C2 P1
U1 IO25 - U2 PWMA
C4 P2 - U4 VSS
C4 P2 - U4 VSS
U1 IO14 - U2 AIN2
U1 IO25 - U2 PWMA
U1 EN - R1 P2
U3 SW - L1 1
U1 IO13 - U2 BIN2
U3 SW - L1 1
U4 VIN - C7 P2
GND
C4 P2 - U4 VSS
U1 GND - U2 GND
U1 IO27 - U2 AIN1
U3 FB - R2 P2
J3 Center pin - C1 P1
U4 VIN - C7 P2
U2 BO1 - J2 P1
U1 3V3 - C2 P1
U1 IO27 - U2 AIN1
U4 VIN - C7 P2
C4 P2 - U4 VSS
C4 P2 - U4 VSS
U2 VM3 - C9 P1
U4 VIN - C7 P2
U1 GND - U2 GND
C4 P2 - U4 VSS
U1 3V3 - C2 P1
C4 P2 - U4 VSS
C9
Capacitance
100nF
C6
Capacitance
220uF
U1
C2
Capacitance
100nF
J3
U4
C8
Capacitance
10uF
C4
Capacitance
100nF
C3
Capacitance
100nF
C7
Capacitance
10uF
C1
Capacitance
1000uF
J2
R3
Resistance
10kΩ
U3
R1
Resistance
10kΩ
D1
L1
Inductance
47uH
R2
Resistance
31.6kΩ
J1
U2

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