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Thermal Validation Controller — Project Specification
1. Objective
Design a build-ready thermal validation controller for the Si-MP-ARRAY-A12 sample. The board shall acquire eight thermocouple channels and safely control one 24 V resistive heater at up to 5 A (120 W).
2. First-Revision Scope
  • One PCB using an ESP32-DevKitC-32E module as the host controller.
  • Eight independent MAX31856 thermocouple digitizer channels.
  • Eight K-type miniature thermocouple sockets with thermocouple-alloy contacts.
  • One low-side PWM heater output rated for 24 VDC, 5 A continuous maximum.
  • Onboard conversion from 24 V input to 5 V for the ESP32 development module.
  • Clean 3.3 V sensor rail.
  • Hardware-latched heater shutdown independent of firmware.
  • USB programming/debug access through the ESP32 development module.
3. Functional Architecture
3.1 Controller
  • Host: ESP32-DevKitC-32E, non-PSRAM variant.
  • SPI bus:
    • SCK: GPIO18
    • MISO: GPIO19
    • MOSI: GPIO23
    • SPI mode 1
    • Initial clock: 1 MHz
  • Chip-select allocation:
    • CH0: GPIO16
    • CH1: GPIO17
    • CH2: GPIO21
    • CH3: GPIO22
    • CH4: GPIO25
    • CH5: GPIO27
    • CH6: GPIO32
    • CH7: GPIO33
  • Heater command: GPIO26.
  • Hardware-fault status input: GPIO34 with an external pull-up.
  • Manual reset input/status may be observed by the MCU, but shall not depend on a boot-strapping pin if a safer free GPIO is available after final pin review.
3.2 Thermocouple Acquisition
  • Digitizers: eight MAX31856 devices, one per channel.
  • Default firmware configuration: K-type.
  • Firmware may configure each channel independently for supported MAX31856 thermocouple types.
  • Each channel shall include datasheet-compliant input filtering and protection selected for thermocouple accuracy and expected cable environment.
  • Cold-junction measurement regions shall be protected from heater-path, regulator, MOSFET, and ESP32 heat sources.
  • Thermocouple connectors shall be mounted together along a board edge in a thermally uniform region.
  • Use one continuous ground reference unless component documentation establishes a specific alternative. Do not create a casually split ground plane.
3.3 Heater Output
  • Load: one 24 VDC resistive heater.
  • Maximum continuous current: 5 A.
  • Maximum nominal power: 120 W.
  • Switching topology: low-side N-channel MOSFET.
  • MOSFET shall have:
    • At least 60 V VDS rating preferred for 24 V switching margin.
    • RDS(on) explicitly characterized at a gate voltage compatible with the selected gate-drive circuit.
    • Adequate pulse, SOA, and thermal ratings at 5 A continuous and selected PWM frequency.
  • Use a dedicated gate driver if direct 3.3 V GPIO drive cannot guarantee low loss and controlled switching.
  • Gate network shall include a series resistor and a default-OFF pull-down.
  • Heater connector and input connector shall each be rated above the protected circuit current with suitable temperature margin.
  • High-current paths shall use copper pours rather than narrow traces, with current and temperature rise verified against the final stackup and copper weight.
  • Provide appropriately rated transient suppression. A flyback diode is required only if the selected heater/cabling presents meaningful inductance; any diode used must be rated for the actual current and repetitive PWM stress.
3.4 Hardware Safety Interlock
  • Any asserted MAX31856 FAULT output shall force the heater command OFF without firmware participation.
  • Fault aggregation shall preserve the polarity and electrical behavior specified by the MAX31856 datasheet; do not use the preliminary BAT54S network without verification.
  • A hardware latch shall retain the OFF state after a fault.
  • The latch may be cleared only by a deliberate manual reset action when the initiating fault is no longer active.
  • Power-up, ESP32 reset, disconnected MCU, and unprogrammed MCU states shall all leave the heater OFF.
  • The ESP32 shall be able to read the aggregate fault/latch state for logging.
  • Firmware may request heater operation but shall not be able to bypass an active hardware fault.
4. Power Architecture
  • Primary input: regulated 24 VDC external supply sized for heater load plus controller margin.
  • Protected heater branch: input fuse sized from connector, wiring, MOSFET, and heater requirements; provisional target is approximately 6.3–8 A pending fuse derating and inrush analysis.
  • Logic branch: protected 24 V-to-5 V buck converter.
  • 5 V output shall support ESP32 peak radio current and downstream logic with design margin.
  • MAX31856 devices operate from a low-noise 3.3 V rail.
  • Determine whether the ESP32 module’s onboard 3.3 V regulator has sufficient thermal/current margin; otherwise provide a separate 3.3 V regulator for sensors.
  • Include reverse-polarity protection, input surge/transient suppression, bulk capacitance, and local high-frequency bypassing.
  • Avoid back-powering conflicts between USB and onboard 5 V power through an explicit power-OR or isolation arrangement.
5. Decoupling and Signal Integrity
  • Each MAX31856 shall receive local ceramic bypass capacitance placed directly at its supply pins, plus local or grouped bulk capacitance based on datasheet guidance.
  • Prefer X7R/X5R ceramic bulk capacitors unless a verified requirement favors tantalum.
  • Route SPI as a short shared trunk with controlled stubs; series damping footprints shall be available at the controller for SCK and MOSI if edge-rate testing requires them.
  • At 1 MHz, formal controlled-impedance routing is not required for SPI, but return-path continuity and clean routing remain mandatory.
  • Keep thermocouple inputs away from PWM gate/drain nodes, the buck converter switch node, ESP32 antenna/radio region, and high-current loops.
6. PCB and Mechanical Requirements
  • Initial target: two-layer PCB, subject to placement/routing feasibility and noise review. Upgrade to four layers if continuous return paths, thermal isolation, or routing density cannot be achieved robustly.
  • Keep the ESP32 antenna region at the board edge with the module manufacturer’s copper/component keepout.
  • Place all eight K-type sockets along a common edge.
  • Locate the buck converter and heater power stage at the opposite side from the thermocouple connectors.
  • Provide test points for 24 V, 5 V, 3.3 V, ground, aggregate fault, latch state, heater command, and switched heater node.
  • Clearly mark thermocouple polarity, channel number, 24 V input polarity, heater output, fuse rating, and safety warnings on silkscreen.
  • Use mounting holes and connector clearances appropriate for a bench/chamber instrument; exact board dimensions remain to be established during layout.
7. Firmware Requirements
  • Initialize all channels as K-type by default.
  • Support independent thermocouple type selection per channel.
  • Poll and log temperature, cold-junction temperature, open-circuit state, and configured fault flags.
  • Drive the heater only after successful startup self-test and confirmed inactive hardware latch.
  • Use bounded PWM and temperature limits; loss of communications or software watchdog reset shall result in heater OFF.
  • Manual reset shall not automatically resume heating; firmware must require a separate valid enable command.
8. Verification and Acceptance Criteria
  • All eight channels enumerate and return plausible ambient measurements with K-type probes.
  • Open-probe and configured over/under-temperature faults latch the heater OFF through hardware.
  • Heater remains OFF during power-up, firmware upload, ESP32 reset, watchdog reset, and MCU removal/disconnection.
  • Manual reset cannot clear the latch while a fault remains asserted.
  • Full-load heater test: 24 V, 5 A continuous at worst-case ambient without exceeding component, connector, fuse, or PCB temperature limits.
  • Logic rails remain within tolerance during ESP32 radio bursts and heater PWM switching.
  • Thermocouple readings remain within the defined accuracy target during heater switching; final numeric accuracy target requires calibration and system-level test definition.
  • ERC and DRC pass with no unexplained violations.
9. Open Engineering Items to Resolve During Detailed Design
  • Select and verify the exact 24 V input connector, heater connector, fuse, TVS, reverse-polarity device, buck converter, MOSFET/gate driver, and safety-latch logic.
  • Select an available PCB-mount K-type miniature socket with verified footprint and alloy contacts.
  • Confirm MAX31856 FAULT output polarity/type and design a correct eight-channel aggregation circuit.
  • Set heater PWM frequency based on heater dynamics, emissions, MOSFET loss, and measurement interference.
  • Establish enclosure, board dimensions, mounting-hole pattern, operating ambient range, thermocouple cable lengths, and required absolute accuracy.
  • Perform power budget, thermal calculations, protection coordination, and layout-current verification before release.
10. Deliverables
  • Fully annotated schematic organized into power, controller, eight-channel sensing, interlock, and heater-output blocks.
  • Complete BOM with manufacturer part numbers, ratings, and purchasable footprints.
  • PCB placement and routing with verified keepouts, current paths, thermal separation, and test access.
  • ERC/DRC review and documented resolution.
  • Bring-up and safety-validation plan.
  • Firmware pin map and initialization notes.

  • 1. Objective

  • 2. First-Revision Scope

  • 3. Functional Architecture

  • 3.1 Controller

  • 3.2 Thermocouple Acquisition

  • 3.3 Heater Output

  • 3.4 Hardware Safety Interlock

  • 4. Power Architecture

  • 5. Decoupling and Signal Integrity

  • 6. PCB and Mechanical Requirements

  • 7. Firmware Requirements

  • 8. Verification and Acceptance Criteria

  • 9. Open Engineering Items to Resolve During Detailed Design

  • 10. Deliverables