Low-Power Sensor Node Design
Thought for 16 sec
Yes — for the minimum add-on parts, that list is reasonable:
Minimum extra parts
Table
| Qty | Part | Recommendation |
|---|---|---|
| 1 | Generic Capacitor | 10 µF on the 5 V rail |
| 1 | Generic Capacitor | 100 nF on the 5 V rail |
| 1 | U1 | PC817B is a good choice |
| 1 | 1N4148 | relay flyback diode |
So you have two valid options:
Simplest answer
If you’re ordering today, I’d say:
If you want, I can give you the exact placement for those two capacitors next.
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Design Notes
Architecture
- Controller: ESP32-WROOM 3.3 V development board
- Mains input/output: two 3-position terminal blocks for Hot, Neutral, and Protective Earth
- Switching: relay switches AC Hot only; Neutral and PE pass through directly
- Accessory ports: two side-mounted USB-C female connectors used for power only
- Accessory LED modules are series-wired and require only power and ground
Default design choices
- Use an isolated AC-DC module to generate low-voltage power from mains
- Use a 2-layer board to make mains creepage and clearance easier to inspect
- Keep mains on outer layers only
- Keep a minimum 6 mm separation between mains and SELV areas
- Route USB-C ports as power-only interfaces with no data routing
Open assumptions used for implementation
- USB-C accessory ports provide a low-voltage power rail and ground only
- No USB PD negotiation or data connectivity is implemented
- Relay contact path switches Hot only
- Neutral and Ground are unswitched pass-through conductors
Schematic implementation notes
- AC_IN uses J1 where Pin_1=Hot, Pin_2=Neutral, Pin_3=PE
- AC_OUT uses J2 where Pin_1=Hot, Pin_2=Neutral, Pin_3=PE
- K1 switches Hot only: J1 Pin_1 -> K1 COM and K1 NO path -> J2 Pin_1
- PS1 is powered from mains Hot and Neutral and generates the 5 V low-voltage rail
- ESP1 is powered from the 5 V input pin on the dev board and uses IO23 for relay control
- J3 and J4 are power-only USB-C ports with 5.1k pull-down resistors on CC1 and CC2
- D+/D-, SBU, and other non-power USB-C signals are intentionally unused
Layout notes
- Board outline revised to 76.2 mm x 127 mm (3 in x 5 in)
- Keep a clear mains zone around J1, J2, K1, and the primary side of PS1
- Keep the ESP32 and USB-C accessory circuitry in the SELV zone
- Put J3 on the left edge and J4 on the right edge
- Maintain a 6 mm isolation corridor between mains and SELV areas where practical
- J1, J2, K1, and PS1 now have explicit 6 mm keep-out reinforcement for mains spacing
- AC_HOT_IN, AC_NEUTRAL, and AC_PE nets are assigned 1.2 mm trace width targets for short mains runs
- Relay coil net is kept narrower and separate from the mains contact routing
Outstanding work
- Remaining airwires still require manual or autorouted trace completion
- Final DRC review should be repeated after routing to verify the mains isolation boundary remains clean
Architecture
Default design choices
Open assumptions used for implementation
Schematic implementation notes
Layout notes
Outstanding work
