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Design Notes
Power Architecture Assumptions
- Primary input: 9 V to 18 V DC through a barrel jack.
- Auxiliary/service input: USB-C 5 V sink-only.
- Main regulated rail: 5 V sized for up to 2 A from the buck stage.
- Battery support: single-cell Li-ion / LiPo charger with system power-path.
- Battery-backed rail: 3.3 V for logic and housekeeping loads.
Implemented Schematic Topology
- Protected DC input path
- Barrel jack -> resettable fuse -> PMOS reverse-polarity stage -> TVS -> bulk/input bypass -> TPS5430 input.
- PMOS gate clamp uses a 12 V zener to protect VGS on the 9-18 V input path.
- 5 V buck rail
- [U1] TPS5430DDA wired with L1 = 18 uH, D3 = MBRA340T3G, C3 = 10 nF bootstrap, R1 = 10 k, R2 = 3.24 k, and C4/C5 on the 5 V output.
- [J4] is tied to the dedicated 5V buck output rail.
- USB-C auxiliary input
- USB-C sink-only with R4/R5 = 5.1 k CC pull-downs to ground.
- VBUS protection uses F2, D2, C6, and C7 before the OR-ing PMOS stage.
- Source OR-ing into charger input
- The buck 5 V rail and protected USB 5 V rail both feed SYS_5V_IN through PMOS ideal-diode style stages (Q3 for buck, Q2 for USB).
- This keeps the charger input rail separate from the main 5 V output connector.
- Charger / power-path defaults
- [U2] BQ24074 is wired with:
- USB500 default mode using EN2 = low and EN1 tied high to SYS_OUT.
- R7 = 1.8 k on ISET -> approximately 494 mA fast-charge current.
- R12 = 3 k on ITERM -> approximately 50 mA termination target.
- R13 = 33 k on TMR for a mid-range safety timer setting.
- R8 = 1.13 k remains populated on ILIM.
- R10/R11 = 100 k pull-ups for ~PGOOD and ~CHG.
- ~CE tied low for default enabled charging.
- SYS_OUT feeds the LDO and any battery-backed housekeeping loads.
- [U2] BQ24074 is wired with:
- Battery and TS path
- BAT goes to [J3] battery positive and C9.
- TS is routed to the battery connector NTC pin and RT1 to ground so the input never floats.
- 3.3 V rail
- [U3] MIC5504-3.3 is fed from SYS_OUT.
- C11 is the LDO input capacitor, C12/C13 are the output capacitors, and [J5] is tied to 3V3.
Charge-Current / Thermal Notes
- Initial R7 = 1.5 k would have programmed about 593 mA, which was inconsistent with the chosen USB500 default mode.
- The design was corrected to R7 = 1.8 k for about 494 mA.
- Estimated worst-case linear-charger dissipation at VIN = 5 V:
- VBAT = 3.0 V -> about 0.99 W
- VBAT = 3.7 V -> about 0.64 W
- This is acceptable for a conservative default but still warrants thermal copper and vias under the charger during layout.
Review Notes
- ERC is clean except for one remaining warning on a duplicate J1:GND pin exposed by the barrel-jack symbol. The tool only exposes a single
J1:GNDidentifier, so the extra duplicate pin could not be independently targeted. Treat this as a symbol-level artifact to revisit if the connector symbol is later replaced.
Next Layout Intent
- Use a 4-layer stackup with a solid ground reference plane.
- Keep the buck hot loop compact.
- Place USB-C protection and the charger close to J2.
- Keep battery traces short and wide between U2 and J3.
- Give the charger and buck thermal copper area plus thermal vias.
Power Architecture Assumptions
Implemented Schematic Topology
Charge-Current / Thermal Notes
Review Notes
Next Layout Intent
