Design Notes
Finalized 2 kW / 100 kHz Power Stage
- Topology locked as 2-phase interleaved asynchronous boost.
- Operating target: 20 V to 40 V turbine input, 48 V charge bus, 2 kW output, 100 kHz PWM per phase.
- Input current range used for sizing: 50 A at 40 V up to 100 A at 20 V.
- Per-phase average input current target: about 25 A to 50 A.
- Duty cycle range: about 0.545 at 40 V input to about 0.706 at 20 V input.
- Ripple target used for magnetics sizing: about 20 percent worst-case per-phase current ripple.
Calculated targets
- Per-phase ripple current target worst case: 10 A at 20 V input.
- Required inductance for 10 A ripple at 20 V, D = 0.706, f = 100 kHz: about 14.1 uH.
- Required inductance for 5 A ripple at 40 V, D = 0.545, f = 100 kHz: about 43.6 uH.
- Final nominal design value chosen: 15 uH per phase as the practical compromise, accepting lower ripple at high line and about 9.4 A ripple worst case at low line.
- Estimated MOSFET current for loss sizing: about 25 A RMS per phase worst practical operating point.
- Conduction loss estimate with 12 mOhm class MOSFET: about 7.5 W per MOSFET.
- Added switching-loss allowance with 65 nC class gate charge and 30 ns edge estimate: about 0.12 W, so the selection remains conduction-loss dominated.
- Output capacitance target from ripple sizing alone is modest, but bulk was increased for transient energy storage and battery-current smoothing.
Final component decisions
- Q1 and Q2: replace 650 V placeholders with 100 V-class low-Rds(on) MOSFETs. Selected library part: NCEP0178AK.
- L1 and L2: set to 15 uH nominal target, >=40 A saturation and current-rating intent, very low DCR magnetics required.
- C13: 470 uF / 50 V input bulk.
- C17 and C18: 10 uF / 50 V high-frequency input bypass MLCCs.
- C14: 470 uF / 63 V output bulk.
- C15 and C16: 2.2 uF / 100 V switch-loop bypass capacitors.
- C19: 4.7 uF / 100 V fast output bypass.
- R7 and R8: 3.3 ohm gate resistors as initial efficiency-oriented value.
Integration notes
- Existing U6 dual isolated driver remains the preferred 100 kHz gate driver.
- U5 fast overcurrent trip path to U6 DIS remains preserved.
- U3 and U4 current-sense amplifiers remain tied to the shunt architecture.
- Existing ADC voltage sensing and filtered fault-monitor path remain unchanged.
Open validation items
- Flux library did not contain a strong direct 15 uH / 40 A single inductor match, so L1 and L2 remain generic inductors with finalized electrical targets.
- Thermal validation required for MOSFET copper area and heatsinking because about 7 W to 8 W per switch is expected near worst case.
- Simulate one phase and then the full 2-phase averaged system for current ripple, bus ripple, and duty-cycle margin.
- Layout must keep the Q-D-L-D-C hot loops compact and use wide copper or pours for turbine and charge-current paths.
System Requirements
- Input source: wind turbine rectified DC bus, 20-40 V, up to 2000 W
- Output target: charge a 48 V power bank
- Required functions:
- Step-up conversion from turbine bus to battery charging bus
- Intelligent load selection based on turbine operating state
- Startup / cut-in behavior to avoid stalling the turbine
- Active power tracking during normal operation
- Battery-limited operation when the power bank cannot accept more power
- Diversion / protection mode for full-battery or fault conditions
- Overcurrent, overvoltage, thermal, and reverse-flow protection
Chosen Architecture
- High-power synchronous boost converter stage for 20-40 V input to regulated 48 V bus
- MCU-based supervisory control for state machine and load-selection algorithm
- Dedicated current/voltage sensing on turbine input and battery/output path
- Diversion-load control path to absorb excess wind power when charging must stop or be reduced
- Protection stage at turbine input and output, including surge clamp, reverse blocking, and current limiting
Operating Modes
- Startup / cut-in: light load, allow rotor acceleration
- Active tracking: adjust boost demand to maintain efficient turbine operating point
- Battery-limited: obey battery charging limits while maintaining safe turbine loading
- Diversion / protection: route excess power to dump load and protect the turbine / converter
Implementation Notes
- This is a conceptual high-power controller architecture prepared for later detailed simulation and component sizing.
- Because the power level is 2 kW, final component ratings, thermal design, magnetics, and PCB copper geometry must be verified in a later pass.
- A 4-layer layout is the minimum sensible stackup for this design due to high current, multiple power domains, and noise control.
Added Schematic Blocks
- Supervisory MCU: STM32F303CBT6
- Gate driver: IR2110STRPBF
- Current sensing: INA196 on turbine input and charging/output path
- Hardware overcurrent trip: INA200D comparator monitor
- Conceptual power stage: external MOSFET pair, boost inductor, input/output bulk capacitors, current shunts
- ADC monitoring: turbine current, charge current, turbine voltage, battery voltage, fault monitor voltage
- MCU control nets: PWM high, PWM low, gate shutdown, overcurrent fault input
Current Limitations
- The present schematic is a functional block-level controller architecture, not yet a final manufacturable 2 kW converter design.
- The boost switch arrangement, inductor value, compensation network, switching frequency, current-loop design, deadtime, and MOSFET ratings still need dedicated power-stage engineering.
- The battery interface is represented as a generic 48 V charge output rail; exact battery chemistry profile and BMS interaction remain to be defined.
100 kHz Interleaved Refinement
- Topology refined from a single conceptual boost phase into a 2-phase interleaved boost stage.
- Design target remains 20-40 V input, 48 V class battery charging output, 2 kW power transfer, and 100 kHz switching priority with efficiency favored.
- Worst-case input current at 20 V and 93% assumed efficiency is approximately 107.5 A total.
- Estimated battery-side current at 54 V output is approximately 37.0 A.
- A 20% per-phase ripple target gives an initial inductance estimate of roughly 5.9 uH at 20 V input and 9.6 uH at 40 V input, so 8.2 uH per phase is being used as a practical placeholder.
Added Refinement Blocks
- Second interleaved inductor phase: L2
- Dedicated boost rectifiers: D1 and D2
- Stronger dual-channel gate driver for 100 kHz switching: U6
- Gate shaping and default-off network: R7, R8, R9, R10
- Additional high-frequency bypass capacitors on input, output, and driver rails: C15, C16, C17, C18, C19, C20, C21
- Filtered protection telemetry placeholder: R11 and C22
Power-Stage Integration Notes
- L1 and L2 form two boost phases from the turbine input rail.
- Q1 and Q2 are low-side boost switches for the two phases.
- D1 and D2 rectify each phase into the battery-side output rail.
- U6 now provides the preferred high-current gate-drive path for phase A and phase B PWM operation at 100 kHz.
- U5 hardware overcurrent output is wired into the fast gate-disable path so firmware-independent shutdown can inhibit the gate driver.
Layout, EMI, and Thermal Direction
- Use short, tightly contained high-di-dt loops for each phase: input bypass -> inductor -> MOSFET -> ground return.
- Keep each diode, MOSFET, and local bypass capacitor cluster physically compact.
- Route gate-drive traces short and away from current-sense and ADC inputs.
- Maintain dedicated quiet analog ground references for sense amplifiers before joining the power ground.
- Reserve copper area and heatsinking strategy for Q1, Q2, D1, D2, L1, and L2.
Validation Benchmarks
- Efficiency target for later validation: prioritize operation above 93% near nominal power if device selection and magnetics permit.
- Verify dead time, switch-node ringing, and gate-drive overlap at 100 kHz.
- Verify inductor current sharing between phases and confirm no excessive saturation risk.
- Measure output ripple, thermal rise of switches/diodes/inductors, and hardware fault response during overcurrent events.