Diagram

• Use the user-specified net names exactly.
• Add TP3 on VBAT_RAW, TP4 on SYS_RAW, TP5 on 5V_REG, TP6 on GND.
• Use left-to-right schematic organization following power flow.
• J1 MPN corrected to EX80-54P-SH(70).
• J1 requires a custom footprint; it is not available as a standard library footprint and needs manual land-pattern creation from the Hirose datasheet.
• J1 pin row mapping intent: Row A (signal), Row B (signal/GND), Row C (VBAT/GND).
• U1 ~PGD is routed to TP8 on net PGD_MON for debug monitoring.
• U4 ALERT/RDY is intentionally NC; explicit no-connect marker still requires manual placement.
• J1 reserve pins are intentionally NC; explicit no-connect markers still require manual placement.
• Remaining ERC warnings after this pass are tool-limitation artifacts rather than intended design behavior errors.
• Substitution recorded: the requested NTMTSC4D2N10GTXG MOSFET was not available in the library, so a 100V class placeholder N-channel MOSFET was used for Q1 pending exact-part replacement.
• Remaining open items from the source requirements are exact values/part choices for C1, C3, R9, and the final J1 pin map for all unassigned docking pins.
• TP8 note: LM5060 Power Good output, active-low. Monitor during debug. NC in normal operation.

• Add a battery voltage monitor sheet that imports 5V_REG, SYS_RAW, and GND from Sheet-A.
• Generate a dedicated 3.3V monitor rail for the ADC using U3.
• Sense SYS_RAW with a 330k / 30k divider, 100nF filter, and 1k series protection into an ADS1115 ADC.
• Export the ADC I2C signals through J8 for NanoPi connection.

• Divider ratio = 30k / (330k + 30k) = 1/12
• V_SYS_RAW ~= V_AIN0 x 12.0
• Range: SYS_RAW 20-36V -> AIN0 1.67-3.0V

• VBAT_MON is high-impedance: keep the trace short and terminate close to the ADS1115 AIN0 input.
• Place the ADS1115 away from the TPS54560 PH switching node on Sheet-A.
• NPI_SDA and NPI_SCL are 3.3V logic only; do not expose them to 5V_REG.
• No I2C pull-up resistors are added on this board because the NanoPi R3S provides on-board 2.2k pull-ups.
• Add 100nF ceramic decoupling on U3 input and output to GND.

• Add detect straps for PLD_DTCT# and INTERPOSER_DTCT# using shared net labels only.
• Add reserve CTRL, USB, and ETH headers using existing shared nets from the EX80 connector.
• Keep GND as the only power rail used on this sheet.

• R10 and R11 are 0 ohm DNP options. When loaded, the associated detect signal is pulled to GND and reads as detected. When DNP, the signal remains floating/open for the undetected state.
• TP1 is placed on PLD_DTCT# and TP2 is placed on INTERPOSER_DTCT# for debug access.
• J3 carries PAYLOAD_SDA, PAYLOAD_SCL, RESET_IN#, and GND.
• J5 carries USB0D_P, USB0D_N, USB0_VBUS, and GND.
• J6 carries MXA_P/N, MXB_P/N, MXC_P/N, and MXD_P/N. No Ethernet termination is added on this board.
• USB0D_P and USB0D_N are a USB 2.0 differential pair and should be routed as a matched pair on the layout.
• MXA through MXD are GigE differential pairs. Target 100 ohm differential impedance on the layout and route matched-length adjacent pairs.
• RESET_IN# is active low. No pull-up is added on this board because the EX80 side provides the pull-up behavior.
• All Sheet-C signals connect by shared labels only; no additional power rails are introduced.