ESP32-S3 Board Design

flux

Reconciled: the executor completed without changing the live result—still 13 airwires and only the J1 warning, with no new copper defects. Since the same worker is stalled on the layer-selection fault, I’m switching to a fresh layout executor to independently diagnose that root cause and attempt the remaining routes without disturbing the clean checkpoint.

flux

The independent recovery pass is still actively working, not stalled or failed. I’m keeping it isolated from the validated USB/power routing and will reconcile its result against live DRC before accepting any changes.
Thought for 4 mins 53 sec
Awaiting 1 background task
Received notification from "PCB Routing Recovery" that it finished — picking the work back up.

flux

The independent PCB routing-recovery executor completed, but I can’t inspect or reconcile its final changes because no ACUs are currently available.
Last verified state before that pass:
  • 12 × 80 mm, four-layer PCB
  • 13 airwires: 12 GPIO nets plus RF net 1
  • 0 dangling traces, copper overlaps, or invalid-layer errors
  • One non-blocking J1 edge-placement warning
Remaining: inspect the recovery report, rerun live DRC, verify USB/RF/crystal/power integrity, and fix or document any residual connections.
Review routing recovery
Check critical routing
Resolve J1 warning
Document routing status
Sign up to send

Files

Schematic

Layout

Preview

Firmware Getting Started
Toolchain
  • Install ESP-IDF for ESP32-S3.
  • Target: esp32s3.
  • Configure flash size for the ESP32-S3FN8 integrated 8 MB flash.
  • Use native USB Serial/JTAG for flashing and logging.
Programming Sequence
  1. Connect USB-C.
  2. Normal programming should enumerate through native USB Serial/JTAG.
  3. If recovery is needed, hold BOOT (GPIO0 low), pulse RESET, then release BOOT.
  4. Flash with idf.py -p flash monitor.
Pin Map

Table

Board signalESP32-S3 pinNotes
USB_D−GPIO19Native USB Serial/JTAG; do not repurpose
USB_D+GPIO20Native USB Serial/JTAG; do not repurpose
BOOTGPIO0Strap; low during reset enters download mode
RESETCHIP_PUActive low hardware enable/reset
J3 GPIO1GPIO1General GPIO / ADC
J3 GPIO2GPIO2General GPIO / ADC
J3 GPIO4–14GPIO4–14General GPIO; ADC/touch functions vary by pin
J3 GPIO15XTAL_32K_P / GPIO15Available only because no 32 kHz crystal is fitted
J3 GPIO16XTAL_32K_N / GPIO16Available only because no 32 kHz crystal is fitted
J3 GPIO17GPIO17General GPIO
J3 GPIO18GPIO18General GPIO
J3 GPIO21GPIO21General GPIO
Minimal ESP-IDF Configuration
  • Enable USB Serial/JTAG console.
  • Keep GPIO19/20 assigned to USB.
  • Do not drive strapping pins externally during reset.
  • Treat GPIO15/16 as ordinary GPIO only while the external 32 kHz oscillator remains unused.
Example GPIO Bring-Up
C
#include "driver/gpio.h"

void app_main(void) {
    gpio_config_t io = {
        .pin_bit_mask = 1ULL << 4,
        .mode = GPIO_MODE_OUTPUT,
        .pull_up_en = 0,
        .pull_down_en = 0,
        .intr_type = GPIO_INTR_DISABLE,
    };
    gpio_config(&io);
    gpio_set_level(GPIO_NUM_4, 1);
}
Startup Order
  1. ROM boot and strap sampling.
  2. Clock and flash initialization.
  3. USB Serial/JTAG console.
  4. Configure only the GPIOs required by the application.
  5. Initialize Wi-Fi/Bluetooth after power and clock are stable.
Cautions
  • GPIO0 is not a general-purpose breakout pin in this design.
  • GPIO19/20 are reserved for USB.
  • GPIO15/16 cannot be used if a future revision adds a 32.768 kHz crystal.
  • RF calibration data and regulatory settings must match the final antenna and enclosure.

  • Toolchain

  • Programming Sequence

  • Pin Map

  • Minimal ESP-IDF Configuration

  • Example GPIO Bring-Up

  • Startup Order

  • Cautions