ESP32-S3 Board Design

flux

The board is now 12 × 80 mm and the route has progressed from 83 to 17 airwires. I’m keeping the layout worker focused on closing those final GPIO/USB connections and then validating edge clearance and copper integrity.

flux

Resized and reworked the PCB into a 12 × 80 mm, four-layer narrow layout, placed all 44 components across both sides, added copper planes, and reduced routing from 83 to 17 airwires at the last verified checkpoint.
Open items
  • Verify the executor’s final routing result and current DRC counts.
  • Close any remaining GPIO/USB airwires and copper/edge-clearance errors.
  • Independently review USB, RF, crystal, regulator, and ground-return routing.
  • Create bring-up, firmware, and compliance project files.
Work paused because the account has no available ACUs.
Received notification from "ESP32 PCB Layout" that it finished — picking the work back up.

flux

The PCB layout executor has finished, but I can’t inspect or reconcile its final report because the account currently has no available ACUs.
Current last-verified state: 12 × 80 mm, four-layer board, all 44 components placed, copper planes added, and routing reduced from 83 to 17 airwires. Remaining work is to verify the executor’s final airwire/DRC counts, inspect USB/RF/crystal/power routing, fix any residual violations, and generate bring-up/firmware/compliance documentation.
Inspect layout status
Review critical routing
List remaining work
Prepare bring-up plan
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Files

Schematic

Layout

Preview

Board Bring-Up Plan
Before Power
  • Inspect QFN orientation, exposed-pad soldering, USB connector, buck inductor, crystal, and u.FL.
  • Check resistance from USB_VBUS to GND and 3V3 to GND for shorts.
  • Confirm DNP USB shunt capacitors C17/C18 are not populated.
First Power
  1. Use a current-limited 5 V bench source or protected USB source.
  2. Set current limit near 100 mA initially.
  3. Verify USB_VBUS appears at J1 and after the fuse at USB_5V_PROTECTED.
  4. Verify the buck output is approximately 3.318 V with no excessive current.
  5. Raise current limit only after the rail is stable.
Rail Checks
  • 3V3: 3.0–3.6 V, target about 3.318 V.
  • 3V3_RF: within a few millivolts of 3V3 at idle.
  • CHIP_PU: rises high after the RC delay; reset button pulls it low.
  • BOOT_GPIO0: normally high; boot button pulls it low.
USB Bring-Up
  • Connect to a host and confirm native USB Serial/JTAG enumeration.
  • Confirm both plug orientations work.
  • Flash a minimal ESP-IDF image.
  • Check D+/D− eye/signal integrity if cable compatibility is inconsistent.
GPIO Checks
  • Toggle each of the 18 breakout GPIOs and verify at J3.
  • Confirm J3 pin 1 is 3V3 and pin 2 is GND.
  • Verify GPIO15/16 operation only with 32 kHz crystal support disabled.
RF Bring-Up
  • Connect a known 50 Ω 2.4 GHz antenna or test fixture to u.FL before transmitting.
  • Verify crystal frequency error under Wi-Fi test mode.
  • Tune C15/C16 to bring frequency error within the required tolerance.
  • Measure the RF network with a VNA and tune C19/L3/C20 for the actual board stackup and enclosure.
  • Perform output-power, harmonics, sensitivity, coexistence, and antenna-efficiency tests.
Pass/Fail Criteria
  • No abnormal heating or rail collapse during Wi-Fi TX.
  • 3V3 remains within the ESP32-S3 operating range during worst-case RF bursts.
  • USB enumeration and flashing are reliable in both Type-C orientations.
  • Reset and boot controls operate repeatedly.
  • All 18 GPIO breakout signals match firmware control.
  • RF/crystal measurements meet the product's regional compliance and performance targets.
Stop Conditions
Stop testing if 3V3 exceeds 3.6 V, QFN/buck components heat rapidly, current rises unexpectedly, or RF transmission is attempted without a proper 50 Ω load/antenna.

  • Before Power

  • First Power

  • Rail Checks

  • USB Bring-Up

  • GPIO Checks

  • RF Bring-Up

  • Pass/Fail Criteria

  • Stop Conditions