MCP73831 Pin Function Guide
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Below is a summary table describing each pin from the MCP73831 family datasheet (DS20001984H):
Table
| Pin | Function | Characteristics and Usage | Special Considerations |
|---|---|---|---|
| PROG | Current Regulation Set and Charge Control Enable | Input pin that requires a resistor from PROG to Vss to enable charging. When the PROG pin is allowed to float or driven to a logic-high, the device is disabled, terminating the charge cycle and reducing the supply current to about 25 µA. Typical programming resistor range is 2 kΩ to 10 kΩ. | Selecting the proper resistor value is essential to set the charge current. Ensure no stray conditions force the pin high if charging is intended. |
| STAT | Charge Status Output | Output pin used for indicating the battery charge status. It can drive an LED or interface to a microcontroller. The MCP73831 provides a tri-state output for STAT while the MCP73832 offers an open-drain configuration. A pull-up resistor can be used for proper interfacing if needed. | A bypass capacitor (minimum 4.7 µF) is recommended to ensure loop stability when the battery is disconnected. |
| VDD | Battery Management Input Supply | Input power supply pin. It powers the device and controls the charging sequence. The device automatically enters a power-down mode if the VDD voltage falls below the UVLO (VSTOP) threshold. Recommended range is from VREG (typical) + 1V up to 6V. | Ensure that VDD always remains above the UVLO level to keep the device active and prevent unnecessary battery drain. |
| BAT (VBAT) | Battery Detection and Charge Control Output | Sources a typical current of 6 µA to detect the presence of a battery. When the battery voltage is below the threshold (factory set to VREG + 100 mV typical), the device assumes a battery is connected and may begin in preconditioning (trickle charge) mode. | The impedance seen by the BAT/VBAT pin must be greater than 7 MΩ to ensure proper battery detection. |
| PGND (Vss/EP) | Ground / Exposed Thermal Pad | Serves as the system ground. The Exposed Thermal Pad (EP) is internally connected to Vss and must be tied to the same potential. This connection ensures proper operation and helps with thermal management of the device. | For improved thermal performance, it is recommended to add vias from the EP land area to an opposing copper layer on the PCB. EP and Vss must share a common ground. |
This table encapsulates the key pin functions, their typical operating modes, and any special considerations highlighted in the datasheet.
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