ESP32 PCB Design for Pulse Control
0:16
Work done
- Renamed the project to ESP32 Golf Ball Dispenser Interface and updated the description for the new single-input golf ball dispenser board.
- Refactored the schematic around U1 to keep the protected 12 V to 24 V input chain, preserve the 5 V then 3.3 V rails through U2 and U3, and keep optional UART access on J3.
- Reworked the field I/O to one conditioned coin pulse input on J1 using Q1, R1, R3, R5, and C9.
- Added the relay output path with K1, Q2, D3, and R2, plus retained the open-collector output on Q3 and assigned J2 as relay NO/COM/NC plus OC_OUT.
- Added SW1 as the user-select switch input to the ESP32 and updated the internal design documentation with the new ESP32 pin mapping and architecture.
- Reapplied the required 100 mm x 80 mm rectangular layout and Standard 4 Layer stackup, then exported updated Gerbers.
Success criteria review
- ✅ The schematic now reflects the new golf ball dispenser concept: one conditioned pulse input, protected power entry, relay dry-contact path, open-collector output, ESP32-WROOM control, and optional UART access.
- ✅ The layout size is set to 100 mm x 80 mm with a 4-layer stackup.
- ✅ Updated Gerber files were generated: esp32-golf-ball-dispenser-interface-gerbers.zip
- ❌ The layout is not yet complete for manufacturing: DRC still reports 42 airwires, so routing and placement cleanup remain.
- ❌ ERC still reports 21 floating pins, including unused ESP32 pins and two spare terminal positions on J1.
- ❌ A BOM export file could not be generated in this run, so the final BOM deliverable is still missing.
Next steps
The remaining work is PCB placement and routing cleanup plus ERC cleanup so the board can be exported as a fully manufacture-ready package. I can continue by reducing the floating-pin warnings, tightening the connector assignments, and preparing the final BOM export once the export issue is resolved.
Revise schematic first
Document pin mapping
Check existing board
17 days
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Design Notes
System Architecture
- Controller: ESP32-WROOM module on custom PCB, no dev board.
- Power input: 12 V nominal to 24 V DC maximum via screw terminal.
- Power protection: reverse-polarity protection, TVS on VIN, bulk input capacitance, buck conversion to 5 V, local regulation to 3.3 V for ESP32.
- Input: 1 protected and opto-isolated coin pulse input intended for a noisy nonstandard source around 6 V idle and 4 V active, with tolerance for approximately 3 V to 12 V+ wiring environments.
- Outputs: 1 SPDT relay dry-contact output and 1 open-collector output, both under ESP32 control.
- Mode selection: 2-position hardware switch read by the ESP32 for user-selectable output behavior.
- Connectors: screw terminals for all field wiring. Optional UART programming header retained only as an internal service connector.
- PCB zoning: power, logic/RF, and field I/O sections separated.
Default Engineering Choices
- Use an optocoupler on the pulse input for robust unknown-source compatibility and ESP32 GPIO protection.
- Use a dedicated SPDT relay for dry-contact output and a separate open-collector transistor output for maximum interface compatibility.
- Drive the relay from the 5 V rail with a discrete NPN transistor and flyback diode.
- Provide a 5 V intermediate rail from the buck converter, then derive 3.3 V locally for the ESP32.
Selected Parts
- U1: ESP32-WROOM-32E-N16
- U2: LMR50410Y5FQDBVRQ1 fixed 5 V buck regulator
- U3: ME6211C33M5 3.3 V LDO regulator
- D1: SMBJ26A input TVS diode
- D2: SS14 series reverse-polarity Schottky diode
- Q1: PC817 optocoupler for isolated pulse input
- Q3: DTC123YKAT146 pre-biased NPN transistor for open-collector output
- Q2: MMBT3904LT1G relay driver transistor
- K1: G5LE-1-DC5 5 V SPDT relay
- D3: 1N4148WX-TP relay flyback diode
- SW1: DSIC02LS-P 2-position mode select switch
ESP32 Pin Mapping
- IO34: Coin pulse input sense
- IO25: Relay control output
- IO26: Open-collector output control
- IO32: Mode select switch position B
- IO33: Mode select switch position A
- IO0: Boot strap / programming header
- EN: Enable / reset header access
- TXD0, RXD0: UART programming and debug
Implementation Notes
- Buck regulator uses a dedicated bootstrap capacitor between CB and SW.
- Pulse input uses one optocoupler with a series resistor, 3.3 V pull-up, series GPIO resistor, and local filter capacitor at the isolated logic node.
- Relay coil is powered from 5 V and switched on the low side by Q2 with D3 across the coil.
- Open-collector output remains a low-side sink intended for external pull-ups.
- J2 is assigned as: pin 1 relay NO, pin 2 relay COM, pin 3 relay NC, pin 4 open-collector output.
Layout Review Findings
- Layout size target remains 100 mm x 80 mm with a Standard 4 Layer stackup.
- Current layout density is low at about 24.5 percent fill, so placement can be improved without changing board size.
- Active DRC shows 38 airwire errors and 1 overlapping-copper error, so the layout is not yet fabrication-ready.
- Existing copper rules are minimal: universal keepout is about 3.8 mil and default traces are 10 mil with 0.15 mm minimum width.
- Remaining ERC warnings are floating unused GPIO pins on the ESP32 module and are not the main fabrication blocker.
Current Blockers To Resolve
- Unrouted PCB connections across the updated power, input, relay, open-collector, and programming sections.
- At least one copper short associated with the Q1 area according to DRC.
- Layout still needs re-placement to clearly preserve zoning between the ESP32/RF area, power entry, pulse input isolation, relay section, and field outputs.
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