INA219 Current Measurement Audit

P

piero789

AUDIT AND FIX ONLY THE PCB ROUTING AROUND Q2 INPUT REVERSE-POLARITY PROTECTION.
Context: The schematic has just been corrected:
  • Q2:D -> VIN_FUSED
  • Q2:S -> VIN_PROTECTED
  • Q2:G -> VIN_GATE
  • D6:K -> VIN_PROTECTED
  • D6:A -> VIN_GATE
  • R5 from VIN_GATE to GND
  • R6 between VIN_PROTECTED and VIN_GATE
Task:
  1. Review the PCB layout only around Q2, F2, D3, D6, R5, R6, C7, FB2, and the nets VIN_RAW, VIN_FUSED, VIN_PROTECTED, VIN_GATE, GND.
  2. Remove any stale traces caused by the Q2 source/drain swap.
  3. Reroute Q2 input-protection traces so the physical PCB matches the corrected schematic.
  4. Keep the current protection sequence: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.
  5. Keep Q2, D3, C7, and FB2 routing reasonably short and direct.
  6. Do not modify ESP32, relay, INA219, buck output, RELAY_OUT, or dry-contact nets.
  7. Do not perform a full board redesign yet.
After fixing:
  • Run DRC.
  • Confirm there are no airwires in the Q2/F2/D3/D6/R5/R6/C7/FB2 input-protection area.
  • Confirm there are no dangling traces in the Q2 input-protection area.
  • Report the exact physical routing path from J1 P1 to U1 VIN after the fix.
  • Confirm again that reverse-polarity input cannot energize VIN_PROTECTED or 5V.

flux

I've made a plan and started work on it.

Started implementing a plan

#Goal

- Audit and fix the PCB routing around the Q2 input reverse-polarity protection stage based on the schematic correction, concentrating only on Q2, F2, D3, D6, R5, R6, C7, FB2 and nets VIN_RAW, VIN_FUSED, VIN_PROTECTED, VIN_GATE, and GND. The goal is to remove stale traces from the Q2 source/drain reversal and reroute the protected input path so that it physically follows the path: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED, while ensuring the routing remains short and direct without impacting other nets (ESP32, relay, INA219, buck output, RELAY_OUT, dry-contact).

#Implementation plan

1. **Audit and Cleanup**

1. Inspect the existing PCB layout in the Q2 input reverse-polarity area to identify stale traces and artifacts from the old Q2 source/drain swap.

2. Remove or sever stale traces that connect the Q2 source/drain paths from previous routing.

2. **Reroute Input-Protected Path**

1. Reroute the protected input path to ensure the physical trace follows: J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.

2. Maintain a short and direct routing while connecting the nets correctly.

3. Preserve the integrity of other nets and components including ESP32, relay, INA219, buck output, RELAY_OUT, and dry-contact.

3. **DRC Verification and Reporting**

1. Run a targeted Design Rule Check (DRC) focusing on the audited area to ensure clearance and connectivity rules are met.

2. Document and report the exact physical routing path and confirm that the reverse-polarity protection works as intended (i.e. reverse-polarity does not pass through VIN_PROTECTED into the remainder of the circuit).

#Success criteria

- All stale traces from the Q2 source/drain swap are removed without affecting other board areas.

- The physical routing path exactly follows J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED, ensuring short and direct routing.

- DRC reports no violations in the scoped area and confirm reverse-polarity behavior as expected.

- The protected input path prevents undesired conduction during reverse polarity events.

Task unable to complete.

2:13

Thought for 16 sec — Identifying necessary skills
Looking up PCB routing cleanup stale traces Q2 reverse polari....
Checking 5 design areas.
Reading schematic details for J1, F2, Q2 and 7 more.
Completed 5 design checks — found 39 issues.
Checking 5 design areas... (28 sec)
Reading layout details for Q2, F2, D3 and 5 more.

flux

Work done
  • Audited the scoped Q2 input-protection area and verified the corrected schematic connectivity.
  • DRC still reports scoped layout problems: VIN_FUSED airwire between F2:P2 and Q2:D, VIN_PROTECTED airwires involving Q2:S, D6:K, and R6:P2, plus stale/dangling trace remnants and an overlap at Q2:D.
  • Created the detailed status file: Q2 Input Protection Routing Remediation Status.
Success criteria review
  • ❌ Stale traces were identified but not removed in this run.
  • ❌ The physical path is not yet fully routed as J1 P1 -> F2 -> VIN_FUSED -> Q2 -> VIN_PROTECTED -> D3/C7/FB2 -> VIN_FILTERED.
  • ❌ DRC is not clean in the scoped area; airwires/dangling/overlap issues remain.
  • ✅ The corrected schematic topology still supports reverse-polarity blocking, but the PCB must be cleaned/rerouted before fabrication.
Next steps
Perform the physical trace cleanup/reroute in the PCB editor for the listed scoped items, then rerun DRC to confirm the Q2 input-protection area is clear.
Locate routing issues
Fix Q2 remnants
Route VIN_PROTECTED
Run targeted DRC
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Files

Schematic

Layout

Preview

U2
U6
R1
Resistance
1kΩ
R3
Resistance
4.7kΩ
C5
Capacitance
100nF
R4
Resistance
4.7kΩ
RSHUNT
Resistance
0.22 Ω
R5
Resistance
100kΩ
R6
Resistance
100kΩ
C3
Capacitance
100nF
C4
Capacitance
100nF
FB2
C7
Capacitance
100nF
RELAY_OUT
J1
F2
K1
L1
Inductance
68uH
D3
D1
Q1
D2
D6
Q2
C2
Capacitance
100uF
R2
Resistance
10kΩ
U1
C1
Capacitance
100uF
Relay / INA219 Shunt Fix
Definitive schematic correction implemented for future orders:
  • Added RSHUNT as a 0.22 Ω, 1%, 0.25 W, SMD 1206 shunt resistor.
  • Connected RSHUNT:P1 to 5V, the same net as U6:IN+.
  • Connected RSHUNT:P2 to RELAY_COIL_HIGH_SENSE, the same net as U6:IN- and K1:A1.
  • Relay low-side drive remains unchanged: K1:A2 connects to RELAY_COIL_LOW, with D1:anode and Q1:C.
  • Q1:E remains on GND; Q1:B remains driven through R1 with R2 pulldown.
  • Flyback diode orientation remains correct: D1:cathode on 5V, D1:anode on RELAY_COIL_LOW.
Correct topology:
Text
5V / U6:IN+ -> RSHUNT -> RELAY_COIL_HIGH_SENSE / U6:IN- / K1:A1
K1:A2 -> Q1:C
Q1:E -> GND
D1 cathode -> 5V side
D1 anode -> relay low side
With an estimated relay coil current of about 70 mA:
  • Shunt drop: 0.07 A × 0.22 Ω ≈ 15 mV
  • Shunt power: 0.07² × 0.22 ≈ 1.1 mW
  • 0.25 W rating is ample.
Layout note:
RSHUNT has been placed near U6 to keep the INA219 sense loop short. Before manufacturing, reroute the PCB so the new physical current path is implemented: 5V -> RSHUNT -> RELAY_COIL_HIGH_SENSE -> K1:A1. The current review still reports layout routing issues after adding/moving the shunt, so do not manufacture until routing is updated and DRC is clean again.