PCB Schematic Creation Request
Execution stopped due to insufficient credits.
2:28
Started: adding gate networks and i2c pullups
Looking for "recommended connection for Sleep pin and no connect pins in typical application" in REF19XSERIES.pdf
Looking for "PCA9685 output structure LEDn pins and OE pin default usage" in PCA9685.pdf
5 days
0:00
Work done
- Retrieved the current schematic state and confirmed the previously missing passive network was in fact absent, not just differently named
- Added the full missing gate-drive and pull-up network: R_G1 through R_G6, R_PD1 through R_PD6, and optional I2C pull-ups R_I2C_SDA and R_I2C_SCL
- Verified key pin details needed for the next wiring pass, including duplicate-name handling on OC1, OC2, OC3, and dual-GND pins on U2 and U3
- Confirmed from the U4 datasheet that
~Sleep~should tie toVinwhen unused, and that TP/NC pins remain explicit no-connects
Success criteria review
- ✅ The missing passive network that blocked progress is now added to the schematic
- ✅ Datasheet-driven tie-off decision for U4 is resolved
- ❌ The board is not yet fully wired
- ❌ ERC/schematic completeness review is not yet finished
- ❌ PCB preparation has not started
Next steps
The immediate next step is to run one full connection pass for power, grounds, I2C, SPI, stepper drivers, MOSFET outputs, the U4 block, and the isolated optocoupler section, then review remaining ERC findings. After schematic completion, the natural next stage is PCB layout: board sizing, stackup, and component placement.
5 days
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TRIBO-ELEK-012 – Auxiliary Module PCB Specification
Projekt: PROD-TRIBO – Tribo-Teststand
Dokument-Nr.: TRIBO-ELEK-012
Revision: 0.3
Erstellt: 2026-04-21 | Überarbeitet: 2026-04-22
Status: Entwurf — für Schaltplanagent (PCB-Generierung)
Referenzen: [IO] TRIBO-ELEK-002 Rev 1.7 · [BOM] TRIBO-ELEK-008 Rev 2.7 · [SUB] TRIBO-ELEK-007 Rev 3.2
Dokument-Nr.: TRIBO-ELEK-012
Revision: 0.3
Erstellt: 2026-04-21 | Überarbeitet: 2026-04-22
Status: Entwurf — für Schaltplanagent (PCB-Generierung)
Referenzen: [IO] TRIBO-ELEK-002 Rev 1.7 · [BOM] TRIBO-ELEK-008 Rev 2.7 · [SUB] TRIBO-ELEK-007 Rev 3.2
1. Zweck
A-AUX erweitert A-MAIN (ESP32) um: PCA9685 PWM (I2C), 5× IRF3708 MOSFET-Treiber (LED/Lüfter), 2× A4988 Stepper (M4/M5), REF195 5V-Referenz, RTC (HW-111), SD-Karte (SPI), K3-Relaistreiber und 3× PC817 Optokoppler (24V PELV → 3,3V Rückmeldung). Alle I2C-Geräte teilen einen Bus.
K3 ist eine informative Temperaturbetriebssperre (kein ISO 13849).
2. Spannungsversorgung
| Netz | Quelle | Spannung | Verwendung |
|---|---|---|---|
+12V | J1 (PSU2 MDR-60-12) | 12 V | MOSFET-Drain, A4988 VMOT, REF195 VIN, K3-Spule |
+5V | J2.5 (A-MAIN 12→5V, >2 A) | 5 V | PCA9685 V+, ADS1256-Modul VCC (via J4) |
+5V_REF | U4 REF195 | 5,000 V | ADS1256 AVDD, FS20, FZB-20N (via J4) |
+3V3 | J2.1 (A-MAIN) | 3,3 V | PCA9685 VCC, A4988 VDD, SD, RTC, Logik |
IO_B4 | J2.6 (A-MAIN MCP23017) | 3,3 V | K3-Relaistreiber Q6 Gate |
GND | Sternpunkt J1.2 | — | Gemeinsame Masse |
Sternpunkt-GND neben J1. REF195 AGND separat zum Sternpunkt führen — keine Motorströme durch Analogbereich.
3. Komponentenliste
Aktive Bauelemente
| Pos. | Bauteil | Gehäuse | Anz. | Funktion / Konfiguration |
|---|---|---|---|---|
| U1 | PCA9685PW | TSSOP-28 | 1 | I2C 0x40; VCC=3,3V; V+=5V; OE→GND; gemeinsamer Bus mit MOD1 |
| U2 | A4988 Pololu | 2×8 SIL | 1 | M4 Linearantrieb; VMOT=12V; VDD=3,3V |
| U3 | A4988 Pololu | 2×8 SIL | 1 | M5 Ölpumpe; DIR+/EN fest GND |
| U4 | REF195GSZ | SO-8 | 1 | VIN=12V → VOUT=5,000V; IOUT≤30mA |
| Q1–Q3 | IRF3708PBF | TO-220 | 3 | LED R/G/B; Gate ← PCA9685 CH4–6 via RG |
| Q4–Q5 | IRF3708PBF | TO-220 | 2 | Lüfter M3a/M3b; Gate ← PCA9685 CH2–3 via RG |
| Q6 | IRF3708PBF | TO-220 | 1 | K3-Treiber; Gate ← IO_B4 (J2.6) via RG6; Q6 nahe Q1–Q5 platzieren |
| OC1–3 | PC817 | DIP-4 | 3 | 24V PELV → 3,3V: Endlage, E-Stop, Tür |
| MOD1 | HW-111 (DS3231) | 4-Pin | 1 | RTC, I2C 0x68, gesteckt; gemeinsamer Bus mit U1 |
| MOD2 | SD-Modul 3,3V | 6-Pin | 1 | SPI, gesteckt, CS separat |
Passive Bauelemente
| Pos. | Wert | Anz. | Funktion |
|---|---|---|---|
| RG1–5 | 100 Ω | 5 | Gate-R Q1–Q5 |
| RG6 | 1 kΩ | 1 | Gate-R Q6 (K3, ≪1 Hz) |
| RPD1–6 | 10 kΩ | 6 | Gate-Pull-down → GND |
| C1 | 10 µF/25V Elko | 1 | REF195 Eingang (SMPS-Ripple-Filter) |
| C3 | 10 µF/16V Elko | 1 | REF195 Ausgang (Datenblatt ≥1µF) |
| C5, C6 | 100 µF/25V Elko | 2 | A4988 VMOT je (Pololu-Empfehlung) |
| R_OC1–3 | 3,3 kΩ 1/4W | 3 | PC817 LED; (24−1,2V)/3,3k ≈ 6,9 mA; P=0,16W (63% Nennlast) |
| R_PU1–3 | 4,7 kΩ | 3 | PC817 Kollektor → +3V3 |
4. Steckverbinder-Pinbelegung
J1 — 12V Eingang (2P Schraubklemme)
Pin 1 =
+12V (PSU2) · Pin 2 = GND (Sternpunkt)J2 — I2C + Versorgung + IO_B4 (6P Stiftleiste)
| Pin | Signal | Beschreibung |
|---|---|---|
| 1 | +3V3 | Logik |
| 2 | GND | |
| 3 | I2C_SDA | → U1 (PCA9685) + MOD1 (RTC) |
| 4 | I2C_SCL | → U1 + MOD1 |
| 5 | +5V | → U1 V+ · J4.2 (ADS1256 VCC) |
| 6 | IO_B4 (MCP23017) | → RG6 → Q6.Gate (K3-Treiber) |
J3 — SPI + Steuerlogik (7P Stiftleiste)
| Pin | Signal | Beschreibung |
|---|---|---|
| 1 | GND | |
| 2 | SPI_SCLK | → J4.3 · MOD2.5 |
| 3 | SPI_MOSI | → J4.4 · MOD2.3 |
| 4 | SPI_MISO | ← J4.5 · MOD2.4 |
| 5 | ADS_CS | → J4.6 |
| 6 | ADS_DRDY | ← J4.7 |
| 7 | SD_CS | → MOD2.6 (TBD-1: GPIO#) |
SPI-Bus geteilt: ADS_CS + SD_CS als separate CS-Leitungen. /RESET und /SYNC am ADS1256-Modul auf DVDD hardwired.
J4 — ADS1256-Kabel (8P, ~1,5m geschirmt)
| Pin | Signal | Beschreibung |
|---|---|---|
| 1 | GND | AGND+DGND; am Schirmgeflecht anlegen |
| 2 | +5V | ADS1256-Modul VCC (interner 3,3V-Regler) |
| 3–5 | SCLK / MOSI / MISO | SPI |
| 6 | ADS_CS | |
| 7 | ADS_DRDY | |
| 8 | +5V_REF | REF195 → AVDD + Sensorexzitation |
Kabel: geschirmt (z.B. ÖLFLEX 180 SiZ), Schirm einseitig GND (Schrankseite), ≥0,25 mm²/Ader. Kein separater AGND nötig — SPI-Rücklaufstrom ~1,2 mV GND-Hub, differenzielle Eingänge unterdrücken dies.
J5 — Probenraum (7P Stiftleiste)
| Pin | Signal | Beschreibung |
|---|---|---|
| 1 | +12V_CHAMBER | Ungeschaltete 12V (LED-Anoden, Lüfter+) |
| 2 | GND | Leistungsrücklauf |
| 3 | LED_R | Q1.Drain |
| 4 | LED_G | Q2.Drain |
| 5 | LED_B | Q3.Drain |
| 6 | FAN_M3a | Q4.Drain |
| 7 | FAN_M3b | Q5.Drain |
Low-side: Last+ → +12V_CHAMBER, Last− → Qx.Drain → Source → GND. Keine Freilaufdioden: BLDC-Lüfter haben interne Treiberelektronik. Gesamtstrom ~0,7A — ein +12V- und ein GND-Pin reichen. Lüfter PWM Pin 4 → TBD-8.
J6/J7 — Motorspulen M4/M5 (je 4P)
Pin 1–4 = A4988 OUT1A/1B/2A/2B → Motorspulen. M4 (J6): NEMA17-05GM, 1,68A/Phase. M5 (J7): Ölpumpe.
J8 — Stepper-Logik (6P Stiftleiste)
| Pin | Signal | Ziel |
|---|---|---|
| 1 | GND | |
| 2 | +3V3 | A4988 VDD |
| 3 | STEP_LIN (GPIO12) | U2.STEP |
| 4 | DIR_LIN (GPIO14) | U2.DIR |
| 5 | EN_LIN (GPIO13) | U2./EN |
| 6 | STEP_OIL (IO_B5) | U3.STEP |
U3: DIR + /EN on-board GND.
K3-Polarität (IO_B4 via J2.6): HIGH → Q6 leitet → K3 an → Sperre aufgehoben. LOW/Power-Off → K3 NC schließt → Sperre aktiv.
J9 — TEC-Treiber (4P Stiftleiste)
| Pin | Signal | PCA-CH |
|---|---|---|
| 1 | PWM_PEL1 | CH0 |
| 2 | PWM_PEL2 | CH1 |
| 3 | KPEL1_DIR | CH7 |
| 4 | KPEL2_DIR | CH8 |
Nur Signalleitungen — A-TEC Boards haben eigene Versorgung. K-PEL1/2 Relais (24V, 650Ω) werden auf A-TEC getrieben.
J10 — K3-Relais (2P)
Pin 1 =
Finder 39.11: 12V / 0,2W / 720Ω / 16,7mA. Keine Freilaufdiode — avalanche-rated (EAS=54mJ >> 0,28mJ).
+12V (Spulenplus) · Pin 2 = K3_SW (Q6.Drain)Finder 39.11: 12V / 0,2W / 720Ω / 16,7mA. Keine Freilaufdiode — avalanche-rated (EAS=54mJ >> 0,28mJ).
J11 — OC-Eingänge 24V PELV (4P)
| Pin | Signal | Quelle |
|---|---|---|
| 1 | PELV_GND | PSU3 0V |
| 2 | OC1_IN | S-POS / K4 (TBD-15) |
| 3 | OC2_IN | K1/K2-Spulenpfad |
| 4 | OC3_IN | IDEM Türstatus (TBD-16) |
Keine GND-Brücke zwischen PELV_GND und PCB-GND. Trennung via PC817. Kriechstrecke ≥2 mm.
J12 — OC-Ausgänge 3,3V (3P)
| Pin | Signal | Logik | Bedeutung |
|---|---|---|---|
| 1 | S_ENDSTOP | LOW=Endlage | OC1 |
| 2 | S_ESTOP | LOW=Relais OK | OC2 |
| 3 | S_DOOR | LOW=Tür offen | OC3 |
Alle aktiv LOW (OC sättigt bei 24V-Eingang). GND über J2.2 geteilt — kein eigener GND-Pin nötig.
MOD1 — RTC (4P Buchse): +3V3 · GND · I2C_SDA · I2C_SCL (TBD-9: SQW/INT benötigt?)
MOD2 — SD (6P Buchse): +3V3 · GND · MOSI · MISO · SCLK · SD_CS
5. PCA9685 Kanalzuordnung
| CH | Signal | Ziel |
|---|---|---|
| 0 | PWM_PEL1 | J9.1 → A-TEC 1 |
| 1 | PWM_PEL2 | J9.2 → A-TEC 2 |
| 2 | PWM_FAN_M3a | RG4 → Q4 |
| 3 | PWM_FAN_M3b | RG5 → Q5 |
| 4 | PWM_LED_R | RG1 → Q1 |
| 5 | PWM_LED_G | RG2 → Q2 |
| 6 | PWM_LED_B | RG3 → Q3 |
| 7 | KPEL1_DIR | J9.3 → A-TEC 1 |
| 8 | KPEL2_DIR | J9.4 → A-TEC 2 |
| 9–15 | — | Reserve |
VCC=3,3V · V+=5V · I2C 0x40 (Bus geteilt mit RTC 0x68) · OE→GND · PWM ~1kHz (Prescale=24)
6. Schaltungen
MOSFET-Treiber (Q1–Q5)
PCA9685 OUT ── RGx (100Ω) ── Gate ──┬── RPDx (10kΩ) ── GND
Source ── GND
Drain ── Last (→ +12V)
IRF3708: VGS(th)=1,0–2,5V · RDS(on)=10mΩ @ VGS=4,5V · bei V+=5V → VGS≈4,95V ✓
K3-Treiber (Q6)
IO_B4 (J2.6) ── RG6 (1kΩ) ── Gate ──┬── RPD6 (10kΩ) ── GND
Source ── GND
Drain ── J10.2 (K3-Spule−) +12V ── J10.1 (K3-Spule+)
REF195
+12V ── C1 (10µF) ── U4.VIN U4.GND ── Sternpunkt
U4.VOUT ──┬── C3 (10µF) ── GND
└── +5V_REF ── J4.8
Laststrom: ADS1256 ~3mA + FS20 ~5mA + FZB-20N ~14mA = ~22mA (max 30mA, TBD-11).
Optokoppler (OC1–3)
24V (J11) ── R_OCx (3,3kΩ) ── PC817 Anode Kathode ── PELV_GND (J11.1)
PC817 Kollektor ──┬── R_PUx (4,7kΩ) ── +3V3 Emitter ── GND (PCB)
└── S_xxx → J12 → ESP32 GPIO
IF=6,9mA · P_R=0,16W (63% v. 1/4W) · CTR≥50% → IC≥3,5mA >> 0,7mA (R_PU) → VCE<0,1V ✓
Kriechstrecke ≥2mm, keine gemeinsame GND-Fläche.
Kriechstrecke ≥2mm, keine gemeinsame GND-Fläche.
7. A4988-Konfiguration
U2 (M4 Linearantrieb): STEP=J8.3 · DIR=J8.4 · /EN=J8.5 · /SLEEP+/RESET → +3V3 (10kΩ) · MS1–3=GND (Vollschritt, TBD-3) · VREF≈1,34V (1,68A, RS=0,1Ω) · VMOT=+12V via C5
U3 (M5 Ölpumpe): STEP=J8.6 (IO_B5) · DIR=GND (fest) · /EN=GND (fest) · Rest wie U2 · VREF → TBD-4 · VMOT=+12V via C6
8. Netzliste
NET +12V: J1.1 → U4.VIN → C5.+ → C6.+ → Q1-Q5.Drain → J10.1 → Q6.Drain
NET +5V_REF: U4.VOUT → C3.+ → J4.8
NET +5V: J2.5 → U1.V+ → J4.2
NET +3V3: J2.1 → U1.VCC → U2.VDD → U3.VDD → MOD1.1 → MOD2.1 → R_I2C1/2 → J8.2
NET GND: J1.2 = J2.2 = J3.1 = J4.1 = J5.2 = ... (Sternpunkt)
NET I2C_SDA/SCL: J2.3/4 → U1.SDA/SCL → MOD1.3/4 (R_I2C1/2 → +3V3)
NET SPI_SCLK/MOSI/MISO: J3.2/3/4 → J4.3/4/5 → MOD2.5/3/4
NET ADS_CS: J3.5 → J4.6
NET ADS_DRDY: J3.6 → J4.7
NET SD_CS: J3.7 → MOD2.6
NET STEP_LIN/DIR_LIN/EN_LIN: J8.3/4/5 → U2.STEP/DIR//EN
NET STEP_OIL: J8.6 → U3.STEP (DIR/EN = GND on-board)
NET PWM_LED_R/G/B: U1.OUT4/5/6 → RG1/2/3 → Q1/2/3.Gate → Q.Drain → J5.3/4/5
NET PWM_FAN_M3a/M3b: U1.OUT2/3 → RG4/5 → Q4/5.Gate → Q.Drain → J5.6/7
NET KPEL1/2_DIR: U1.OUT7/8 → J9.3/4
NET IO_B4: J2.6 → RG6 → Q6.Gate
NET K3_SW: Q6.Drain → J10.2
NET M4/M5: U2/U3.OUT → J6/J7.1-4
NET PELV_GND: J11.1 → OC1-3.Kathode
NET OC1-3_IN: J11.2/3/4 → R_OC1-3 → OC1-3.Anode
NET S_ENDSTOP/ESTOP/DOOR: OC1-3.Kollektor (R_PU→+3V3) → J12.1/2/3
9. Layout-Richtlinien
- GND-Sternpunkt bei J1.2. Motorströme getrennt vom Analogbereich.
- REF195 als Analog-Insel. C1/C3 direkt am IC. Kurze Bahn VOUT → J4.8.
- A4988 in Sockeln, C5/C6 direkt an VMOT. Motorleiterbahnen ≥1,5mm.
- MOSFETs TO-220. RGx am Gate-Pin platzieren.
- Leiterbahnbreiten: +12V ≥2mm · Motorspulen/MOSFET-Drain ≥1,5mm · Logik/REF 0,5mm
- I2C Pull-ups R_I2C1/2 (SDA/SCL): Pads vorsehen, nur bestücken wenn A-MAIN keine hat (TBD-6). Ein Bus für PCA9685 + RTC.
- Optokoppler in Reihe am Platinenrand nahe J11/J12. ≥2mm Kriechstrecke PELV ↔ 3V3. Kein Copper-Pour unter OCs.
- M3-Abstandshalter, ≥5mm zum Schrankgehäuse.
10. Offene Fragen
| Nr. | Thema | Prio |
|---|---|---|
| TBD-1 | SD_CS GPIO-Nummer | Hoch |
| TBD-3 | A4988 Mikroschritt MS1–3 | Mittel |
| TBD-4 | M5 Ölpumpe VREF (Motorspec fehlt) | Hoch |
| Gelöst: V+=5V, VCC=3,3V. IRF3708 RDS(on)=10mΩ @ VGS=4,5V ✓ | — | |
| TBD-6 | I2C Pull-ups auf A-MAIN vorhanden? | Hoch |
| Gelöst: Keine Freilaufdioden. Lüfter=BLDC, K3=Avalanche (0,28mJ << 54mJ EAS) | — | |
| TBD-8 | Arctic P12 PWM Pin 4 Beschaltung | Niedrig |
| TBD-9 | HW-111 SQW/INT-Pin benötigt? | Niedrig |
| TBD-11 | REF195 Laststrom bestätigen (FS20+FZB-20N) | Hoch |
| Gelöst: IO_B4 → J2.6 (A-MAIN), STEP_OIL → J8.6. Kein Konflikt mehr. | — | |
| TBD-15 | OC1: S-POS direkt oder K4-Spule? | Hoch |
| TBD-16 | OC3: IDEM KL1-P Kontakttyp (NO/NC)? | Hoch |
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