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Project Specification: 12V SEPIC Converter
Project Overview
Status: Draft / blocked pending controller choice.
Design a 4-layer SEPIC converter PCB for a student EV battery-management project. Input is a 9-15 V DC Li-ion battery pack. Output is regulated 12 V DC at 0.5-1.5 A, 18 W maximum.
Intended Use
Prototype/validation PCB for an electrical engineering student project. Must be hand-solderable and prioritize MOSFET thermal performance over minimum board size.
What the Device Should Do
- Convert 9-15 V DC input to regulated 12 V DC output.
- Support 0.5-1.5 A output current.
- Operate at 340 kHz in CCM.
- Maintain output ripple optional ferrite bead/protection -> SEPIC power stage -> 12 V output.
Control path is currently unresolved: the requested regulated feedback network requires a PWM controller/gate driver with FB/reference/compensation pins, but no controller IC was specified.
Hardware Subsystems
Power Input
- 2-pin terminal block or JST connector rated >=3 A.
- Input rail: 9-15 V DC.
- Optional VIN ferrite bead footprint for EMI mitigation.
SEPIC Power Stage
- Q1: IRLZ44N N-channel MOSFET, 55 V, logic-level, gate drive 10 V.
- D1: SS34 Schottky, 3 A, 40 V.
- L1/L2: separate 100 uH inductors.
- C1: coupling capacitance target 30 uF, 25 V, low ESR.
- C2: output capacitance target 25 uF, 25 V, low ESR.
- Cin: input capacitance target 25 uF, 25 V, low ESR.
Feedback / Control
- Rtop: 190 kOhm, 1%, 0805.
- Rbottom: 10 kOhm, 1%, 0805.
- Optional Cff: 10 pF in parallel with Rtop.
- Controller IC and compensation network are not yet specified.
Interfaces and Connections
- VIN connector: VIN, GND.
- VOUT connector: +12V, GND.
- Gate-drive header: PWM_IN, GND, VCC_10V.
- Optional I2C telemetry header: SCL, SDA, VCC, GND.
- Test points: TP_VIN, TP_VOUT, TP_SW, TP_GND, TP_FB.
Power and Runtime Expectations
- Maximum output power: 18 W.
- Efficiency: 81-84% per MATLAB simulation.
- Worst-case input current at 9 V and 81% efficiency: 18 W / (9 V * 0.81) = 2.47 A.
- Input connector/protection should be rated >=3 A minimum, preferably >=4 A for margin.
Power Tree and Power Budget
Table
| Rail | Voltage | Load / Function | Current |
|---|---|---|---|
| VIN | 9-15 V | SEPIC input power | up to 2.47 A calculated |
| VOUT | 12 V | Load output | 0.5-1.5 A |
| VCC_10V | 10 V | MOSFET gate drive header | 0.3 A specified |
Manufacturing and Assembly Expectations
- 4-layer PCB.
- Board target =3 mm, VOUT >=2 mm, SW >=2 mm and very short.
- Switching loop area target: =3.5 A, but peak switch current is 4.69 A. For >=30% margin, inductor saturation should be at least about 6.1 A, not 3.5 A.
- SS34 current margin should be checked carefully: 3 A rating versus 1.5 A output is 2x nominal, but thermal/current waveform margin depends on layout and duty cycle.
Controller update: TPS55340 was proposed, but datasheet verification shows it is an integrated-switch regulator, not an external MOSFET gate driver. It has no BOOT or PVDD pins and cannot directly drive IRLZ44N. If TPS55340 is used, the external IRLZ44N must be removed and the SEPIC power stage must use the TPS55340 internal 5-A, 40-V switch. If IRLZ44N remains mandatory, a different controller is required.
Feedback update: TPS55340 feedback reference is 1.229 V. The 210 kOhm / 10 kOhm divider would not produce 12 V; it would target about 27 V. A 12 V TPS55340 divider should use approximately 87.6 kOhm over 10 kOhm; TI's SEPIC example uses 86.6 kOhm over 10 kOhm.
Inductor update: saturation-current requirement is now >=6.5 A. No exact Flux-library 100 uH, =6.5 A shielded inductor match was found yet; this may require adding/importing a manufacturer part or selecting an available alternate.
Change Notes
- Initial project requirements captured from MATLAB v7.1 verified specification.
- Project renamed to 12V SEPIC Converter.
- TPS55340 controller request reviewed against datasheet; schematic generation paused pending topology decision because TPS55340 conflicts with mandatory external IRLZ44N use.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Power Input
SEPIC Power Stage
Feedback / Control
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Physical Design Expectations
Important Design Decisions
Assumptions and Open Issues
Change Notes
