Fixing Missing Routed Traces
0:44
Running design review.
Analyzing the schematic.
Analyzing the PCB layout.
Identifying unrouted nets.
Identifying unrouted nets around U1.
I inspected the local schematic and PCB data around U1. For this kind of debug, the right source order is to use schematic, review, and layout inspection together .
What I can tell so far
The DRC confirms there are still 53 airwire errors globally, and U1 is involved in the PCB because its footprint appears in layout and one of the reported problem pads matches the same footprint family seen around it.
The review output does not expose a clean
U1 nets to inspect first
Highest priority: direct off-board / header connections
net -> offending pad mapping, so I can’t name the exact DRC airwire by net from the review alone. But I can identify the U1-connected nets that still need routing attention first.These are the easiest to miss in layout and most likely to remain as visible airwires from U1:
Table
| U1 pin | Net | Other endpoint |
|---|---|---|
| D2 | Net (U1 - D2) | J5 pin 4 |
| D3 | Net (U1 - D3) | J5 pin 5 |
| D4 | Net (D4 - P1) | J5 pin 3 |
| D5 | Net (D5 - P1) | J8 pin 3 |
| D6 | Net (D6 - P1) | J7 pin 3 |
| D0/RX | Net (U1 - D0/RX) | J6 pin 5 |
| D1/TX | Net (U1 - D1/TX) | J6 pin 4 |
| A4 | Net (12C - Pin_3) | 12C pin 3 |
| A5 | Net (A5 - P1) | 12C pin 4 |
| A6 | Net (A6 - P1) | J9 pin 3 |
| A7 | Net (A7 - P1) | J10 pin 3 |
| D12/MISO | Net (U1 - D12/MISO) | EN pin 1 |
These also originate at U1 and are common airwire candidates if routing was only partially completed:
Table
These are power nets, so they may already be connected by broader routing or fills, but still deserve checking:
Table
There is a likely logic conflict in the schematic:
And similarly:
That is not an airwire problem by itself, but it is suspicious and worth verifying before you spend time routing those nets.
Best next check in the editor
In PCB view:
- Turn on Airwires
- Click U1
- Start by tracing these pins visually:
D2,D3,D4,D5,D6,D0/RX,D1/TX,A4,A5,A6,A7 - Then inspect
D7toD11,A0toA3
If you want, I can do the next pass and narrow this further to a shortest “route these first” list based on which U1 nets are most likely still unrouted near the motor-driver area versus the header area.
Prioritize shortest list
Check motor-driver nets
Flag logic conflict
34 days
To get started, talk to Flux or create a New Document.
Welcome 👋
Flux helps you build PCBs faster with an AI teammate!
Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.