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PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_
PA1/OSCI/A1/T1CH2/OPN0
PC3/T1CH3/T1CH1N_/UCTS_
PC7/MISO/T1CH2_/T2CH2_/URTS_
PD6/A6/URX/T2CH3_/UTX
PD2/A3/T1CH1/T2CH3_/T1CH2N_
PC2/SCL/URTS/T1BKIN/AETR_/T2CH2_/T1ETR_
VDD
PC6/MOSI/T1CH1CH3N_/UCTS_/SDA_
PC5/SCK/T1ETR/T2CH1ETR_/SCL_/UCK_/T1CH3_
PC0/T2CH3/UTX_/NSS_/T1CH3_
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_
PD1/SWIO/AETR2/T1CH3N/SCL_/URX_
PD7/NRST/T2CH4/OPP1/UCK_
VSS
PC4/A2/T1CH4/MCO/T1CH1CH2N_
PD3/A4/T2CH2/AETR/UCTS/T1CH4_
PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
PD0/T1CH1N/OPN1/SDA_/UTX_
PD5/A5/UTX/T2CH4_/URX_

RISC_V_Controller