CM5 Ethernet Switch
VBUS_EN/VBAT and U2 VDD12_SW_OUT—plus the incorrect U2/L2 association; placement and copper checks remain clear, with details in ERC Metadata Remediation.Waiting for input
Table
| Item | U2 status and evidence | U3 status and evidence |
|---|---|---|
| EP mask opening | PASS nominal intent / final union NOT VERIFIED. EP winning rule: 8 ×8 mm copper, +0.05 mm mask → 8.10 ×8.10 mm nominal opening. All thermal lands lie inside this opening; per-via tenting cannot prove top holes covered after mask union. | NOT VERIFIED. Native SVG confirms EP 10.50 ×10.50 mm on Top. Exact EP rule-source read has no mask/paste expansion override; footprint-generated values are explicitly excluded by that tool. Cannot infer 10.50 or 10.60 mm actual mask opening from absence of overrides. |
| EP explicit paste count/size | PASS rule geometry: all nine active zones freshly inspected, each 2.30 ×2.30 mm, every combination X/Y −2.65/0/+2.65 mm. EP monolithic paste rule −4.00 mm nominally suppresses 8 mm EP opening. | NOT VERIFIED actual paste. Complete 279-node compact U2/U3 pad/zone inventory lists only nine U2 zones, no explicit U3 paste-window zones. U3 has no project EP monolithic suppression/windowing rule. Asset-derived paste remains unavailable, so absence of standalone zones is not proof of one full EP aperture or no aperture. |
| EP paste coverage | PASS nominal: 9 ×2.30² =47.61 mm² /64 =74.390625%. Matches cited QFN general/encroached ranges. Final union/duplicate asset paste NOT VERIFIED. | NOT VERIFIED. If an unreduced full 10.50 mm square aperture exists it would be 110.25 mm², 100% of copper (110.25% of the 10 mm device EP); this is a conditional risk, not a measured defect. No measured window count, area or duplicate paste union. |
| Window webs / EP containment | PASS nominal: 2.65−2.30 =0.35 mm web; total extent ±3.80 mm leaves 0.20 mm inset from ±4 mm copper. No window overlaps another or crosses EP copper boundary in rule geometry. | NOT VERIFIED: window geometry unavailable, so no web or edge-inset certificate. |
| Perimeter mask / paste attributes | PASS nominal rules: four row rules cover 72 lands, copper 0.30 ×0.90 mm (orientation exchanged by row), mask +0.05 mm →0.40 ×1.00 mm opening, paste expansion zero →0.30 ×0.90 mm. Fresh SVG includes all 72 copper rectangles at 0.50 mm pitch. Runtime/final mask/paste artwork NOT VERIFIED. | NOT VERIFIED mask/paste. SVG includes 128 peripheral copper rectangles, 0.20 ×1.52 mm at 0.40 mm pitch. Full pad inventory enumerated but returns no effective mask/paste values. Do not guess expansion from system defaults. |
| Signal-pad mask dams | PASS nominal, no margin: 0.50−0.40 =0.10 mm within rows, equal to extracted JLC green minimum and above Microchip 0.09 mm. EP-to-row nominal mask gap 4.45−4.05 =0.40 mm; no nominal merging. Actual registration, mask union and neighboring-trace clearance NOT VERIFIED. | NOT VERIFIED. Copper gap 0.40−0.20=0.20 mm. With hypothetical +0.05 mm expansion a dam would be 0.10 mm, but that expansion is not verified. EP copper-to-signal copper minimum axis gap 6.90−5.25=1.65 mm; mask gap cannot be certified. |
| Thermal-via mask treatment | PASS documented tenting intent, physical coverage NOT VERIFIED: corrected 36-carrier rule retains −0.305 mm top and bottom expansion on 0.61 mm lands, nominal zero individual openings. Large top EP mask opening overlaps the entire field. | NOT VERIFIED: 64 GND thermal carriers previously identified; fresh allowance rule only sets viaInPad Through-hole, not top/bottom mask expansion. No project-level U3 tenting rule was found. Asset/default effective openings unavailable. |
| Thermal lands/drills vs EP boundary | PASS lands: independent 36/36 0.61 mm diameter, 1.20 mm pitch; extent ±3.305 mm inside EP ±4 mm (0.695 mm margin). Full 0.33 mm drill inventory NOT VERIFIED: fresh SVG context shows one actual via drill radius0.165 at (−9.4,−1.8), but not all36. Suppressed library MH drills are not substitute evidence. | PASS nominal array containment: existing 8×8 1.20 mm field extends ±4.20 mm; 0.60 mm lands extend ±4.50, within ±5.25 EP (0.75 mm margin). Full current effective drill/mask inventory NOT VERIFIED in this batch. SVG also draws suppressed MH primitives: do not count as active replacement drill or paste evidence. |
| Paste overlaps thermal holes | Conditional overlap established by intended geometry: at local (±0.6,±0.6), central window spans ±1.15 mm and includes intended0.33 mm holes; windows are not hole keepouts. Acceptable filling/capping process must be confirmed, not assumed from tenting. | NOT VERIFIED: paste is unavailable; full-EP conditional aperture would overlap the thermal field. |
| Resin fill / cap / flatness | NOT VERIFIED supplier acceptance for both: approved intent is selective nonconductive epoxy fill + planarization + copper cap, Type VII. Mask tenting and overlap permissions do not implement or prove that process; no communication/acceptance obtained. | Same. |
| Actual Top mask/paste layers | NOT VERIFIED: fresh zone rule-source and compact scene both say Top Solder Paste, but combined native SVG is copper/silk, not a mask/paste-only plot. Earlier computed.layer Top discrepancy remains unresolved; this review does not prove incorrect exported copper. | NOT VERIFIED: native copper SVG is not production paste/mask evidence. No supported layer-specific snapshot input was exposed by inspected get_layout schema; no manufacturing export attempted to bypass unrouted release gates. |
mutate_board custom copper schema exposes role/name/color and numeric weightOz (0.25–6), but no independent copper thickness. Dielectric and mask objects expose thicknessMm; these are not copper inputs. Loose any wrappers do not document backend acceptance of extra fields.get_layout_rule_config reports stackup valueType boardStackup, with top-level version/key/baseTemplateKey/label/layers/vias/holes. It supplies no nested layer field names, units or serializer. Fresh layout scene-tree and full physical-stackup reads return formatted geometry, not writable structured layer JSON. Thus the top-level discovery is insufficient to safely submit a raw custom stackup; no invented copper field or weight conversion was tried.custom-standard-6-layer, Standard 6 Layer (Custom); manufacturing profile Custom (no base), saved stackup none.Table
| Parameter | Before = after, unchanged | Approved JLC06161H-3313 target |
|---|---|---|
| Copper L1/L6 | 0.035 mm | 0.035 mm |
| Copper L2/L3/L4/L5 | 0.035 mm each | 0.0152 mm each |
| L1–L2 / L5–L6 gap | two 0.071 mm Prepreg sheets each, total 0.142 mm; Dk 4.1 | 3313 ×1, 0.09940 mm; Dk 4.1 |
| L2–L3 / L4–L5 gap | Core 0.457 mm each; Dk 4.7 | bare Core 0.55 mm each; Dk 4.6 |
| L3–L4 gap | two 0.071 mm Prepreg sheets, total 0.142 mm; Dk 4.1 | 2116 ×1, 0.1088 mm; Dk 4.16 |
| Roles L1→L6 | Signal / GND / Signal / Power / GND / Signal | preserve same roles |
| Mask | 0.025 mm each side, Dk 4 | not newly approved/changed here |
| Overlay/paste | 0.010 mm each per side | not laminate thickness specifications |
| Via/hole configurations | Through-hole L1→L6 0.60 mm land / 0.30 mm template drill; wildcard drill and laser holes | preserve configurations and node-specific overrides |
Every layer's properties can be modified by clicking on the target property. Some of those properties will have preloaded options, and some others can accept any input.
boardStackup.layers schema, or an exact JLC06161H-3313 saved profile. Specifically require 0.0152 mm inner copper without a nominal weight conversion, preserving six-layer roles, outline, placements, and via configurations. Manual Stackup Editor property editing is documented, but arbitrary exact copper-thickness acceptance is not established; do not claim a manual exact implementation has been verified. After support supplies or applies a supported representation, re-read every physical layer and run bounded stackup validation before any action 3.Table
| Assigned item | Outcome | Evidence / limitation |
|---|---|---|
| Correct U2 thermal rule targeting only | Completed mutation | Existing ruleset c1f38fa7-9dec-4377-8004-e72883ab5c21 selector replaced with 36 exact current Smart Via carrier UID descendant-via selectors. All existing geometry values retained: 0.33 mm hole, 0.61 mm XY land, −0.305 mm top/bottom mask expansion, All annular layers, Through-hole via-in-pad and Direct Connect. No U3/global rule, outline, placement, net or schematic change. Mutation acknowledged success; ruleset readback reports 36-via 6×6 array and intended dimensions. |
| Exhaustive effective child geometry verification | Incomplete / blocked readback | Initial post-change detailed output visibly confirmed corrected U2 children and unchanged U3 samples, but was truncated. Subsequent 100-child readback confirms all 36 selected carrier-derived child UIDs exist among 100 thermal children, yet returns UID-only tables rather than per-child computed values. Compact readback instead groups template defaults 0.30/0.60 mm; do not treat these as effective override measurements. Cannot certify all 36 U2 or all 64 U3 baked values from this final response. Prior full carrier inspection established the U2 Cartesian field X −13/−11.8/−10.6/−9.4/−8.2/−7 and Y −3/−1.8/−0.6/+0.6/+1.8/+3 mm, 1.20 mm pitch. |
| Concrete structured stackup support check | Completed discovery; application failed/blocked | get_layout_rule_config('Stackup') returns canonical stackup, valueType boardStackup, top-level options version/key/baseTemplateKey/label/layers/vias/holes, but no nested copper layer thickness schema. Stackup readback remains Standard 6 Layer (Custom), all copper 0.035 mm, with existing dielectric construction. This discovery does not establish a supported exact writable 0.0152 mm copper representation. No undocumented JSON or weight conversion submitted; physical stackup unchanged. |
| Fresh selected DRC/ERC | Completed, not release pass | reviewedAt 2026-10-06T15:45:47.571Z: selected via-in-pad, overlapping copper, under-connected via and stackup review query returned no violations; Invalid Pads contains one Informational Footprint item a92706e0-4ca5-4f78-bc46-f60b229303ba__afdaecec-4ca5-88aa-bcb5-c3e51085f548. Missing Power still has three Errors: U1:VBUS_EN, U1:VBAT, U2:VDD12_SW_OUT. No suppression or electrical fix authorized. Bounded checks do not certify overall DRC or assembly readiness. |
| Internal platform feedback | Failed submission | Requested explicit independent copper thickness / documented structured stackup layer schema; feedback tool explicitly reported submission failed. No ticket was filed. |
| Routing, placement changes, export, quotes, order | Unattempted | Outside this batch authorization. |
Table
| Check | Status / severity | Fresh evidence and disposition |
|---|---|---|
| U2 nine stencil windows: size, symmetry, web and coverage | Completed / PASS geometry | All nine active zones read 2.30 × 2.30 mm at every combination of local X/Y −2.65, 0, +2.65 mm. Web = 0.35 mm; aperture area = 47.61 mm²; coverage of 8 × 8 mm EP = 74.390625%; edge inset = 0.20 mm. Matches Microchip AN18.15 symmetrical-window recommendation, minimum 0.30 mm web and 65–90% area range. |
| U2 stencil actual layer | Completed inspection / BLOCKED acceptance, Warning | Every zone explicitly says raw layer: Top Solder Paste, but computed.layer: Top. This is not proof of erroneous exported copper, nor proof of correct stencil output. Actual layer-specific production output is required; exports are expressly prohibited in this scope. |
| U2 EP mask/paste rule | Completed rule check / PASS intent, BLOCKED final mask union | EP rule remains +0.05 mm mask (nominal 8.10 mm opening) and −4.00 mm monolithic paste suppression. Its large EP opening includes the entire via field; per-via tenting cannot independently prove holes covered after mask union. Filled/capped treatment remains mandatory. |
| U2/U3 thermal count, pitch, containment, net and span | Completed / PASS geometry | 100 current protected GND Smart Via carriers: U2 36 at X −13, −11.8, −10.6, −9.4, −8.2, −7 mm and Y −3, −1.8, −0.6, +0.6, +1.8, +3 mm; U3 64 at X 9.8 through 18.2 mm and Y −4.2 through +4.2 mm, step 1.20 mm. All connect all six layers. With 0.60 mm lands, U2 copper-field extent is ±3.30 mm inside ±4 mm EP; U3 ±4.50 mm inside ±5.25 mm EP. Direct-connect effective thermal relief. |
| U2 intended 0.33/0.61 mm override effectiveness | Completed / FAIL, Error relative to repair intent | All 100 thermal via children read baked hole 0.30 mm and land 0.60 mm; forceAnnularLayers is Top, Bottom, not All. Current U2 example carrier 04da9dec-9dc2-45a8-b182-ccdc2b950e6d is at (−9.4, −1.8) mm. Existing rule c1f38fa7… still selects old carrier UIDs such as d8a7d489…, absent from the current 100-child UID list. Therefore the documented 0.33/0.61 mm and tenting override is not effective on the current array. Do not copy old drill map into fabrication notes. Repair requires a separately authorized mutation targeting current carriers/children; none made here. |
| Current actual thermal holes/annuli versus published recommendations | Completed / PASS nominal screening, BLOCKED vendor process acceptance | Current 0.30 mm hole / 0.60 mm land gives 0.15 mm radial annulus, matching AN18.15 best-result ranges (0.25–0.30 mm finished hole, 0.5–0.6 mm pad) and 1.20 mm pitch fits 0.8–1.5 mm range. Fits previously sourced JLC POFV 0.20–0.50 mm hole and ≥0.05 mm annulus nominal limits. CAD hole is not verified finished-hole tolerance; filled/capped acceptance and selective fill map still need vendor confirmation. |
| U3 EP copper / GND | Completed / PASS geometry | Exact active EP node at offset 120 of U3 pad list reads 10.50 × 10.50 mm, local (0,0), GND e90050fa…, direct connect. |
| U3 segmented paste and effective mask | Completed bounded inspection / BLOCKED | U3 pad/footprint detail has no exposed effective mask/paste-expansion fields, and combined U2/U3 zone listing returns only nine U2 windows. No U3 segmentation evidence exists in this inspection; absence of standalone zones does not establish absence of asset-derived paste. Need actual asset-derived stencil/mask geometry or authorized production-layer inspection. Do not certify U3 paste coverage or invent its mask expansion. |
| Type VII fill/cap and final flatness | Completed intent comparison / BLOCKED | CAD permissions and raw tenting rules do not implement epoxy fill, planarization or copper caps. Vendor/assembler approval required; AN18.15 paste guidance depends on via treatment, so 74.4% is a sound initial pattern, not an approved Type VII reflow recipe. |
| Ordinary PTH/NPTH clearance around fill arrays | BLOCKED individually | Array spacing is measured, but does not establish the previously sourced >0.45 mm clearance to ordinary drills. Need drill-classified geometry including asset holes and vendor interpretation; no export permitted. |
| Exact approved copper thickness API | Completed schema discovery / BLOCKED implementation | mutate_board custom copper object provides name, color, type and numeric weightOz (0.25–6), not thicknessMm; thicknessMm exists for dielectric and solder-mask objects only. Thus weight is NOT merely an enumeration, but there is no supported independent numerical copper-thickness field. The loosely typed bottom/middle/unchanged wrappers do not establish backend support for extra copper keys. create_stackup_profile accepts only layout UID/name/reason and snapshots current stackup; it cannot supply layer construction. Previously discovered JLC saved profiles are four-layer. Exact 0.0152 mm inner foil cannot be applied with the exposed supported tool contract; no invented conversion or unknown JSON key was submitted. Generic physical stackup stays unchanged. |
Table
| Assigned item | Status | Evidence / specific blocker |
|---|---|---|
| Confirm approved manufacturer construction and available targets | Completed | Fresh official JLCPCB impedance-page inspection confirms JLC06161H-3313 copper 0.035 mm exterior / 0.0152 mm interior; outer 3313 prepreg 0.09940 mm, Dk 4.1; middle 2116 prepreg 0.1088 mm, Dk 4.16; core Dk 4.6. Bare-core 0.55 mm is from the earlier source extraction below. Four discoverable JLCPCB saved stackups are all four-layer, not substitutes for this six-layer build. |
| Apply exact custom physical stackup | Failed / blocked; mutation unattempted | The inspected typed custom-board input exposes copper weightOz, not independently specified copper thickness. The published inner foil is labeled 0.5 oz but is explicitly 0.0152 mm; substituting a generic nominal weight conversion would not verify that geometry. No documented exact representation was established. Current generic custom six-layer stackup, all 0.035 mm copper, remains unchanged; do not report the approved stackup as applied. |
| Record fabrication intent | Completed in this file only | Require ENIG and explicit epoxy fill + planarization + copper caps (Type VII), identifying every active U2/U3 thermal via. This is not an applied native manufacturing profile, selected order option, or production acceptance. Tenting and via-in-pad allowance remain unchanged and are not evidence of Type VII processing. |
| Preserve impedance requirements / establish route geometry | Preservation completed; width/spacing application unattempted and blocked | No net metadata edited. Previously sampled PCIe 85 ohm differential +/-5%, Ethernet 100 ohm differential +/-15%, RGMII 50 ohm single-ended +/-15% remain the requirements. Fresh sampled Ethernet/RGMII readback agrees; query filtering returned a broader scope, not an exhaustive audit. Actual finished copper, pressed construction, mask and calculator settings plus fabricator acceptance of PCIe +/-5% are still required. No verified widths/gaps were generated. |
| Verify thermal-via and stencil readiness | Failed / incomplete | U2 raw rules select 36 thermal carriers, 0.33 mm holes / 0.61 mm lands; U3 via-in-pad allowance remains. Fresh selected U2 paste zones 1/5/9 are active 2.30 mm squares at local diagonal coordinates -2.65/0/+2.65 mm. Their raw layer is Top Solder Paste but computed.layer is Top, so actual stencil-layer output is NOT verified. Full baked U2 via/pitch, U3 mask/paste, final mask union and vendor array acceptance remain open. No footprint repairs were changed. |
| Fresh bounded pre-routing review | Completed, not a release pass | ERC returned three Missing Power Errors: U1:VBUS_EN, U1:VBAT, U2:VDD12_SW_OUT. Airwire-inclusive DRC query reports 375 entries, first 12 shown as Airwire Errors. A separate selection for stackup, board-edge placement, component-body overlap, pad access, overlapping copper and via-in-pad returned no entries; this bounded result is not comprehensive geometric or fabrication certification. |
| Routing, exports, quotes and orders | Unattempted | Outside this approval and still gated. |
custom-standard-6-layer.Table
| Copper layer | Purpose | Copper thickness |
|---|---|---|
| L1 Top | Signal | 0.035 mm |
| L2 Mid-Layer 1 | Ground plane | 0.035 mm |
| L3 Mid-Layer 2 | Signal | 0.035 mm |
| L4 Mid-Layer 3 | Power plane | 0.035 mm |
| L5 Mid-Layer 4 | Ground plane | 0.035 mm |
| L6 Bottom | Signal | 0.035 mm |
PCIE_CM5; RGMII examples TXD0–3/TXC/RXC/RX_CTL 50 Ω single-ended, ±15%, TX/RX bus groups; LAN and WAN MDI examples 100 Ω differential, ±15%, reciprocal partners and per-port bus groups. Prior repair report records an exhaustive 68-net audit; this investigation sampled the current 100-net page rather than claiming a new exhaustive audit.Table
| Stack element, top to bottom | Published thickness | εr |
|---|---|---|
| L1 copper | 0.035 mm | — |
| 3313 ×1 prepreg | 0.09940 mm | 4.1 |
| L2 copper | 0.0152 mm | — |
| Core, without copper | 0.55 mm | 4.6 |
| L3 copper | 0.0152 mm | — |
| 2116 ×1 prepreg | 0.1088 mm | 4.16 |
| L4 copper | 0.0152 mm | — |
| Core, without copper | 0.55 mm | 4.6 |
| L5 copper | 0.0152 mm | — |
| 3313 ×1 prepreg | 0.09940 mm | 4.1 |
| L6 copper | 0.035 mm | — |
Table
| Stack element | Published detail |
|---|---|
| L1/L6 | 0.0175 mm base copper, plated to 1 oz |
| L1–L2 and L5–L6 | PP2116 RC58%, initial 0.1300 mm, pressed 0.1195 mm, Dk 4.45 |
| L2/L3/L4/L5 | 0.0350 mm copper |
| L2–L3 and L4–L5 | Bare core 0.4300 mm, 0.5000 mm including two copper layers, Dk 4.6 |
| L3–L4 | PP7628 RC46%, initial 0.1960 mm, pressed 0.1750 mm, Dk 4.74 |
| Finished board | Catalog states 1.55 mm ±10% |
mfp_stackup-preset-standard-6-layer. Searches for manufacturer-specific JLCPCB and PCBWay manufacturing profiles both returned none. Generic Standard Density described as four-layer must not be called a manufacturer-backed six-layer solution. No currently discoverable one-click manufacturer-backed six-layer target is available. A physical stackup and saved target pointer are independent.Action 3 mask and paste review — 2026-10-07
Source applicability
Finite review table
Confirmed findings, next correction gate, completion
Action 2 checkpoint — 2026-10-07
Supported path versus missing contract
Before / after / approved required geometry
Exact next user action and source evidence
Authorized targeting correction and support check — 2026-10-06
Focused finite-check completion — 2026-10-06
Assembly evidence and platform scope
Approved implementation follow-up — 2026-10-06
Item status
Concrete handoff gates
Recommendation and approval gate
Current live project inspection
Physical stackup — confirmed
Exposed pads, via arrays and stencil — mixed evidence
Impedance metadata — confirmed examples, not routed impedance
Manufacturer-published six-layer choices
JLCPCB exact construction
PCBWay exact construction
Flux target availability — confirmed
Next actions — only after user approval
Scope status and remaining uncertainty