WiFi & Bluetooth Sensor Node
Worked for 4 mins 27 sec
Implemented the schematic for the USB-C powered Wi‑Fi/BLE temperature/humidity node. It uses a SiWG917 Wi‑Fi/BLE 5.4 module, SHT41 T/RH sensor, USB-C sink input, TPS25940 true reverse-blocking eFuse with OVP/UVLO/OCP/soft-start, MP28301 3.3 V buck regulator, ESD protection, reset/ISP/SWD debug, I2C pull-ups, and status LED.
Created project files:
Open items:
- PCB layout/routing is not done yet, so airwire DRC errors are expected.
- Generic passives still need final manufacturer MPNs before manufacturing export.
- Layout must enforce the SiWG917 antenna keepout and thermal isolation around the SHT41.
Suggested next steps:
- Set board size/stackup and move into PCB placement.
- Place U1 at the board edge with antenna keepout and U4 away from heat sources.
- Route power, buck, I2C, SWD/UART, and USB-C protection paths.
- Assign final passive MPNs and run full DRC/manufacturing checks.
Place route and MPNs
Start PCB placement
Assign passive MPNs
Route the PCB
Run full review
Demo Complete
The demo is finished. It didn't use any ACUs. You can now continue working with this project like normal.
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Board Bring-Up Plan — USB-C WiFi BLE TH Sensor
Prerequisites
- Equipment: USB-C current meter or current-limited 5 V supply, DMM, oscilloscope, SWD debugger, 3.3 V USB-UART adapter.
- Firmware: use the Firmware Starter project file.
- Safety: do not exceed normal USB-C 5 V input during initial bring-up. The TPS25940 eFuse is configured for ~1 A current limit, ~4.3 V UVLO, ~6.0 V OVP cutoff, and true reverse-current blocking.
1. Visual Inspection
- Confirm J1 USB-C orientation and shell solder joints.
- Confirm U1 SiWG917 module orientation and antenna edge/keepout in layout.
- Confirm U2 TPS259621, U3 MP28301, U4 SHT41, D1-D4, L1, and polarized LED orientation.
- Inspect for bridges on U1 module castellations/pads and U3 QFN pins.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Tolerance | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|---|
VBUS_RAW | J1 USB-C VBUS | 4.75–5.25 V | USB source | J1 VBUS / U2 IN | Source limited 100–300 mA first power | Present only after USB-C attach |
VBUS_PROT | U2 TPS25940 OUT | ~VBUS minus small drop | <200 mV drop at light load | U2 OUT / C3 | U2 ~1 A limit | No oscillation, no FLT assertion |
3V3 | U3 MP28301 buck OUT1 | 3.3 V | ±5% initial | U3 OUT1 / C5 / U1 VBATT | 700 mA regulator rating | 3.135–3.465 V |
1V8_FLASH | U1 internal 1V8_LDO | ~1.8 V | per module spec | U1 1V8_LDO / C14 | Module internal | Present after U1 powered |
Procedure:
- With no power, measure resistance from
VBUS_RAW,VBUS_PROT,3V3, and1V8_FLASHto GND. - Power from a current-limited 5 V source at 100–300 mA for first power-up.
- Verify
VBUS_RAW, thenVBUS_PROT, then3V3, then1V8_FLASH. - Check
BUCK_SWonly with oscilloscope probe ground kept short; expect switching waveform. - Increase current limit only after no shorts/heating are observed.
3. Critical Signal Verification
Table
| Signal | Expected State | Measure At | Notes |
|---|---|---|---|
EFUSE_EN_UVLO | High when VBUS is valid | U2 EN | R5/R6/R4 divider enables around ~4.3 V rising |
EFUSE_OVP | Below trip during normal USB 5 V | U2 OVP | R5/R6/R4 divider trips around ~6.0 V input |
EFUSE_FLT_N | High when no fault | U2 FLT / U1 UULP_VBAT_GPIO_3 | Open-drain pull-up R7 |
PWR_PGOOD | High when 3.3 V is valid | U3 PG1 / U1 UULP_VBAT_GPIO_2 | Open-drain pull-up R8 |
POC_IN | High after POC_OUT release | U1 POC_IN / SW1 | SW1 pulls low for reset |
RESET_N | High after reset delay | U1 RESET_N / J2 pin 10 | R12/C17 RC |
SWO_ISP | Floating/high unless SW2 pressed | U1 JTAG_TDO_SWO | Hold SW2 during reset for ISP |
4. Connector and Interface Tests
Table
| Connector | Type | Pins to Verify | Test Method |
|---|---|---|---|
| J1 | USB-C receptacle | VBUS, GND, CC1, CC2, shell | Continuity and USB-C attach current check |
| J2 | 10-pin debug header | 3V3, GND, SWDIO, SWCLK, SWO, RESET_N, UART RX/TX | Continuity to U1 and debugger target-detect |
5. Programming and Debug Interface
- SWD: J2 pin 1
3V3, pin 2SWDIO, pin 4SWCLK, pins 3/5/9 GND, pin 10RESET_N. - UART ISP: J2 pin 7
UART_RX_MCU, pin 8UART_TX_MCU; hold SW2 during reset.
Procedure:
- Connect SWD debugger and confirm target voltage is 3.3 V.
- Attempt target detection and read device ID.
- Flash a minimal firmware image that toggles
STATUS_LEDand prints over debug/UART. - Test SW1 reset and SW2 ISP entry.
6. Functional Validation
Table
| Test | Components | Expected Result | Pass Criteria |
|---|---|---|---|
| I2C scan | U1, U4, R9, R10 | SHT41 appears at 0x44 | Address ACKs reliably |
| T/RH read | U4 SHT41 | Plausible indoor readings | Temp within ambient ±2 °C initially; RH 0–100% |
| Status LED | U1, R11, LED1 | LED toggles | Visible without excessive current |
| Wi-Fi | U1 | 2.4 GHz scan/connect | Network scan succeeds |
| BLE | U1 | BLE advertising/provisioning | Advertising visible on phone/sniffer |
| Protection fault | U2 | FLT responds to overload | Use controlled electronic load only |
7. Layout-Sensitive Bring-Up Notes
- Place U1 antenna at board edge and keep antenna clearance free of copper/traces/components on all layers.
- Place U4 SHT41 away from U3 buck, L1, U1, LED1, and USB-C heat sources; consider thermal slots/air gap.
- Keep U3/L1 switching loop compact and away from antenna and sensor.
Pass/Fail Summary
Table
| Section | Result | Notes |
|---|---|---|
| Visual Inspection | [ ] Pass / [ ] Fail | |
| Power Rails | [ ] Pass / [ ] Fail | |
| Critical Signals | [ ] Pass / [ ] Fail | |
| Connectors | [ ] Pass / [ ] Fail | |
| Programming | [ ] Pass / [ ] Fail | |
| Functional Validation | [ ] Pass / [ ] Fail |
Board Status: [ ] Ready for deployment / [ ] Requires rework
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector and Interface Tests
5. Programming and Debug Interface
6. Functional Validation
7. Layout-Sensitive Bring-Up Notes
Pass/Fail Summary
